- slight mips32 cleanup/reformat
- add missing svn props git-svn-id: svn://svn.berlios.de/openocd/trunk@1159 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
ntfreak
parent
3a59ff8bda
commit
8f2c1659cf
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@ -49,36 +49,38 @@ static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
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begin_ejtag_dma_read:
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// Setup Address
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Read & set DSTRT
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/* Initiate DMA Read & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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// Wait for DSTRT to Clear
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/* Wait for DSTRT to Clear */
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do {
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
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// Read Data
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/* Read Data */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, data);
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// Clear DMA & Check DERR
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
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goto begin_ejtag_dma_read;
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} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
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}
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else
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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@ -93,42 +95,46 @@ static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
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begin_ejtag_dma_read_h:
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// Setup Address
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Read & set DSTRT
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/* Initiate DMA Read & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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// Wait for DSTRT to Clear
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/* Wait for DSTRT to Clear */
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do {
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
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// Read Data
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/* Read Data */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Clear DMA & Check DERR
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
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goto begin_ejtag_dma_read_h;
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} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
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}
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else
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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// Handle the bigendian/littleendian
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if ( addr & 0x2 ) *data = (v>>16)&0xffff ;
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else *data = (v&0x0000ffff) ;
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/* Handle the bigendian/littleendian */
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if (addr & 0x2)
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*data = (v >> 16) & 0xffff;
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else
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*data = (v & 0x0000ffff);
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return ERROR_OK;
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}
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@ -141,45 +147,55 @@ static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
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begin_ejtag_dma_read_b:
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// Setup Address
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Read & set DSTRT
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/* Initiate DMA Read & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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// Wait for DSTRT to Clear
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/* Wait for DSTRT to Clear */
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do {
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
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// Read Data
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/* Read Data */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Clear DMA & Check DERR
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
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goto begin_ejtag_dma_read_b;
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} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
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}
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else
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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// Handle the bigendian/littleendian
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switch(addr & 0x3) {
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case 0: *data = v & 0xff; break;
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case 1: *data = (v>>8) & 0xff; break;
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case 2: *data = (v>>16) & 0xff; break;
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case 3: *data = (v>>24) & 0xff; break;
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switch (addr & 0x3) {
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case 0:
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*data = v & 0xff;
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break;
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case 1:
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*data = (v >> 8) & 0xff;
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break;
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case 2:
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*data = (v >> 16) & 0xff;
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break;
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case 3:
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*data = (v >> 24) & 0xff;
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break;
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}
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return ERROR_OK;
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@ -193,37 +209,39 @@ static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
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begin_ejtag_dma_write:
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// Setup Address
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Setup Data
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/* Setup Data */
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v = data;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Write & set DSTRT
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/* Initiate DMA Write & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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// Wait for DSTRT to Clear
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/* Wait for DSTRT to Clear */
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do {
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
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// Clear DMA & Check DERR
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
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goto begin_ejtag_dma_write;
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} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
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}
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else
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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@ -236,44 +254,45 @@ static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
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u32 ejtag_ctrl;
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int retries = RETRY_ATTEMPTS;
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// Handle the bigendian/littleendian
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/* Handle the bigendian/littleendian */
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data &= 0xffff;
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data |= data<<16;
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data |= data << 16;
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begin_ejtag_dma_write_h:
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// Setup Address
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Setup Data
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/* Setup Data */
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v = data;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Write & set DSTRT
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/* Initiate DMA Write & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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// Wait for DSTRT to Clear
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/* Wait for DSTRT to Clear */
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do {
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
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// Clear DMA & Check DERR
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
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goto begin_ejtag_dma_write_h;
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} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
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}
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else
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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@ -286,45 +305,46 @@ static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
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u32 ejtag_ctrl;
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int retries = RETRY_ATTEMPTS;
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// Handle the bigendian/littleendian
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/* Handle the bigendian/littleendian */
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data &= 0xff;
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data |= data<<8;
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data |= data<<16;
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data |= data << 8;
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data |= data << 16;
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begin_ejtag_dma_write_b:
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// Setup Address
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/* Setup Address*/
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Setup Data
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/* Setup Data */
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v = data;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Write & set DSTRT
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/* Initiate DMA Write & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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// Wait for DSTRT to Clear
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/* Wait for DSTRT to Clear */
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do {
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
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// Clear DMA & Check DERR
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
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goto begin_ejtag_dma_write_b;
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} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
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}
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else
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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@ -351,8 +371,8 @@ int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
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int i;
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int retval;
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for(i=0; i<count; i++) {
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if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
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for (i=0; i<count; i++) {
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if ((retval = ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
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return retval;
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}
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@ -364,8 +384,8 @@ int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16
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int i;
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int retval;
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for(i=0; i<count; i++) {
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if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
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for (i=0; i<count; i++) {
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if ((retval = ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
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return retval;
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}
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@ -377,8 +397,8 @@ int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *b
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int i;
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int retval;
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for(i=0; i<count; i++) {
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if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
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for (i=0; i<count; i++) {
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if ((retval = ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
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return retval;
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}
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@ -405,8 +425,8 @@ int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
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int i;
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int retval;
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for(i=0; i<count; i++) {
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if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
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for (i=0; i<count; i++) {
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if ((retval = ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
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return retval;
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}
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@ -418,8 +438,8 @@ int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16
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int i;
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int retval;
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for(i=0; i<count; i++) {
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if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
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for (i=0; i<count; i++) {
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if ((retval = ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
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return retval;
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}
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@ -431,8 +451,8 @@ int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *
|
|||
int i;
|
||||
int retval;
|
||||
|
||||
for(i=0; i<count; i++) {
|
||||
if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
|
||||
for (i=0; i<count; i++) {
|
||||
if ((retval = ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -234,7 +234,7 @@ int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *
|
|||
MIPS32_SW(8,0,15), /* sw $8,($15) */
|
||||
MIPS32_SW(9,0,15), /* sw $9,($15) */
|
||||
MIPS32_SW(10,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $11,($15) */
|
||||
|
||||
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
|
||||
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
|
||||
|
|
@ -308,7 +308,7 @@ int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *
|
|||
MIPS32_SW(8,0,15), /* sw $8,($15) */
|
||||
MIPS32_SW(9,0,15), /* sw $9,($15) */
|
||||
MIPS32_SW(10,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $11,($15) */
|
||||
|
||||
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
|
||||
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
|
||||
|
|
@ -387,7 +387,7 @@ int mips32_pracc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *bu
|
|||
MIPS32_SW(8,0,15), /* sw $8,($15) */
|
||||
MIPS32_SW(9,0,15), /* sw $9,($15) */
|
||||
MIPS32_SW(10,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $11,($15) */
|
||||
|
||||
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
|
||||
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
|
||||
|
|
@ -481,7 +481,7 @@ int mips32_pracc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
|
|||
MIPS32_SW(8,0,15), /* sw $8,($15) */
|
||||
MIPS32_SW(9,0,15), /* sw $9,($15) */
|
||||
MIPS32_SW(10,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $11,($15) */
|
||||
|
||||
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
|
||||
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
|
||||
|
|
@ -536,7 +536,7 @@ int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16
|
|||
MIPS32_SW(8,0,15), /* sw $8,($15) */
|
||||
MIPS32_SW(9,0,15), /* sw $9,($15) */
|
||||
MIPS32_SW(10,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $11,($15) */
|
||||
|
||||
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
|
||||
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
|
||||
|
|
@ -596,7 +596,7 @@ int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *b
|
|||
MIPS32_SW(8,0,15), /* sw $8,($15) */
|
||||
MIPS32_SW(9,0,15), /* sw $9,($15) */
|
||||
MIPS32_SW(10,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $10,($15) */
|
||||
MIPS32_SW(11,0,15), /* sw $11,($15) */
|
||||
|
||||
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
|
||||
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include "types.h"
|
||||
#include "jtag.h"
|
||||
|
||||
/* tap instructions */
|
||||
#define EJTAG_INST_IDCODE 0x01
|
||||
#define EJTAG_INST_IMPCODE 0x03
|
||||
#define EJTAG_INST_ADDRESS 0x08
|
||||
|
|
@ -40,6 +41,7 @@
|
|||
#define EJTAG_INST_TCBDATA 0x12
|
||||
#define EJTAG_INST_BYPASS 0xFF
|
||||
|
||||
/* debug control register bits */
|
||||
#define EJTAG_CTRL_TOF (1 << 1)
|
||||
#define EJTAG_CTRL_TIF (1 << 2)
|
||||
#define EJTAG_CTRL_BRKST (1 << 3)
|
||||
|
|
@ -85,11 +87,15 @@
|
|||
#define EJTAG_DEBUG_DM (1 << 30)
|
||||
#define EJTAG_DEBUG_DBD (1 << 31)
|
||||
|
||||
/* implementaion register bits */
|
||||
#define EJTAG_IMP_NODMA (1 << 14)
|
||||
#define EJTAG_IMP_MIPS16 (1 << 16)
|
||||
|
||||
typedef struct mips_ejtag_s
|
||||
{
|
||||
int chain_pos;
|
||||
u32 impcode;
|
||||
// int use_dma;
|
||||
/*int use_dma;*/
|
||||
u32 ejtag_ctrl;
|
||||
} mips_ejtag_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -256,12 +256,15 @@ int mips_m4k_assert_reset(target_t *target)
|
|||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
|
||||
}
|
||||
|
||||
if (strcmp(target->variant, "ejtag_srst") == 0) {
|
||||
if (strcmp(target->variant, "ejtag_srst") == 0)
|
||||
{
|
||||
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
|
||||
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
|
||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
|
||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
/* here we should issue a srst only, but we may have to assert trst as well */
|
||||
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
|
||||
{
|
||||
|
|
@ -522,7 +525,7 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou
|
|||
case 2:
|
||||
case 1:
|
||||
/* if noDMA off, use DMAACC mode for memory read */
|
||||
if(ejtag_info->impcode & (1<<14))
|
||||
if(ejtag_info->impcode & EJTAG_IMP_NODMA)
|
||||
return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
else
|
||||
return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
|
|
@ -561,7 +564,7 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co
|
|||
case 2:
|
||||
case 1:
|
||||
/* if noDMA off, use DMAACC mode for memory write */
|
||||
if(ejtag_info->impcode & (1<<14))
|
||||
if(ejtag_info->impcode & EJTAG_IMP_NODMA)
|
||||
mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
else
|
||||
mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
|
|
|
|||
Loading…
Reference in New Issue