ARM11 error checking
Øyvind Harboe
parent
20a3b14828
commit
8f09c5df85
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@ -452,7 +452,9 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
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}
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#endif
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arm11_run_instr_data_prepare(arm11);
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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return retval;
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/* save r0 - r14 */
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@ -473,7 +475,9 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
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if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
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{
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/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
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arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
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retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
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if (retval != ERROR_OK)
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return retval;
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}
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else
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{
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@ -483,7 +487,9 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
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/* save CPSR */
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/* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
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arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
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retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
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if (retval != ERROR_OK)
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return retval;
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/* save PC */
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@ -516,11 +522,15 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
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/* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
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/* MCR p15,0,R0,c1,c0,0 */
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arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
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retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
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if (retval != ERROR_OK)
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return retval;
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}
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arm11_run_instr_data_finish(arm11);
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retval = arm11_run_instr_data_finish(arm11);
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if (retval != ERROR_OK)
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return retval;
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arm11_dump_reg_changes(arm11);
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@ -565,8 +575,11 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
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int arm11_leave_debug_state(arm11_common_t * arm11)
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{
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FNC_INFO;
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int retval;
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arm11_run_instr_data_prepare(arm11);
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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return retval;
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/** \todo TODO: handle other mode registers */
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@ -583,7 +596,9 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
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// LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
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}
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arm11_run_instr_data_finish(arm11);
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retval = arm11_run_instr_data_finish(arm11);
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if (retval != ERROR_OK)
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return retval;
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/* spec says clear wDTR and rDTR; we assume they are clear as
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otherwise our programming would be sloppy */
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@ -598,32 +613,44 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
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}
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}
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arm11_run_instr_data_prepare(arm11);
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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return retval;
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/* restore original wDTR */
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if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
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{
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/* MCR p14,0,R0,c0,c5,0 */
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arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
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retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
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if (retval != ERROR_OK)
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return retval;
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}
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/* restore CPSR */
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/* MSR CPSR,R0*/
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arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
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retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
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if (retval != ERROR_OK)
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return retval;
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/* restore PC */
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/* MOV PC,R0 */
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arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
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retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
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if (retval != ERROR_OK)
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return retval;
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/* restore R0 */
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/* MRC p14,0,r0,c0,c5,0 */
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arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
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arm11_run_instr_data_finish(arm11);
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retval = arm11_run_instr_data_finish(arm11);
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if (retval != ERROR_OK)
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return retval;
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/* restore DSCR */
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@ -1260,6 +1287,7 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
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int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
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/** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
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int retval;
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FNC_INFO;
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@ -1273,10 +1301,14 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size,
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arm11_common_t * arm11 = target->arch_info;
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arm11_run_instr_data_prepare(arm11);
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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return retval;
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/* MRC p14,0,r0,c0,c5,0 */
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arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
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retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
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if (retval != ERROR_OK)
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return retval;
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switch (size)
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{
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@ -1335,13 +1367,12 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size,
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}
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}
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arm11_run_instr_data_finish(arm11);
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return ERROR_OK;
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return arm11_run_instr_data_finish(arm11);
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}
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int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int retval;
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FNC_INFO;
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if (target->state != TARGET_HALTED)
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@ -1357,7 +1388,9 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,
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arm11_run_instr_data_prepare(arm11);
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/* MRC p14,0,r0,c0,c5,0 */
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arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
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retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
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if (retval != ERROR_OK)
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return retval;
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switch (size)
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{
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@ -1368,12 +1401,16 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,
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for (size_t i = 0; i < count; i++)
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{
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/* MRC p14,0,r1,c0,c5,0 */
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arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
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retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
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if (retval != ERROR_OK)
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return retval;
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/* strb r1, [r0], #1 */
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/* strb r1, [r0] */
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arm11_run_instr_no_data1(arm11,
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retval = arm11_run_instr_no_data1(arm11,
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!arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
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if (retval != ERROR_OK)
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return retval;
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}
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break;
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@ -1389,12 +1426,16 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,
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memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
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/* MRC p14,0,r1,c0,c5,0 */
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arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
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retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
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if (retval != ERROR_OK)
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return retval;
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/* strh r1, [r0], #2 */
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/* strh r1, [r0] */
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arm11_run_instr_no_data1(arm11,
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retval = arm11_run_instr_no_data1(arm11,
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!arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
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if (retval != ERROR_OK)
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return retval;
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}
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break;
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@ -1410,27 +1451,32 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,
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{
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/* STC p14,c5,[R0],#4 */
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/* STC p14,c5,[R0]*/
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arm11_run_instr_data_to_core(arm11, instr, words, count);
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retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
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if (retval != ERROR_OK)
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return retval;
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}
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else
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{
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/* STC p14,c5,[R0],#4 */
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/* STC p14,c5,[R0]*/
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arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
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retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
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if (retval != ERROR_OK)
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return retval;
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}
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break;
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}
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}
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#if 1
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/* r0 verification */
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if (!arm11_config_memrw_no_increment)
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{
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uint32_t r0;
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/* MCR p14,0,R0,c0,c5,0 */
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arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
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retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
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if (retval != ERROR_OK)
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return retval;
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if (address + size * count != r0)
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{
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@ -1444,11 +1490,8 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,
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return ERROR_FAIL;
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}
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}
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#endif
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arm11_run_instr_data_finish(arm11);
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return ERROR_OK;
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return arm11_run_instr_data_finish(arm11);
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}
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@ -2010,6 +2053,8 @@ arm11_common_t * arm11_find_target(const char * arg)
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int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
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{
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int retval;
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if (argc != (read ? 6 : 7))
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{
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LOG_ERROR("Invalid number of arguments.");
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@ -2055,12 +2100,16 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
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if (read)
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instr |= 0x00100000;
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arm11_run_instr_data_prepare(arm11);
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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return retval;
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if (read)
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{
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uint32_t result;
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arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
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retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
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if (retval != ERROR_OK)
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return retval;
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LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
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(int)(values[0]),
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@ -2071,7 +2120,9 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
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}
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else
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{
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arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
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retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
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if (retval != ERROR_OK)
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return retval;
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LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
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(int)(values[0]), (int)(values[1]),
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@ -2079,10 +2130,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
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(int)(values[2]), (int)(values[3]), (int)(values[4]));
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}
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arm11_run_instr_data_finish(arm11);
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return ERROR_OK;
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return arm11_run_instr_data_finish(arm11);
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}
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int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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@ -247,15 +247,15 @@ void arm11_dump_reg_changes(arm11_common_t * arm11);
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void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
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void arm11_add_IR (arm11_common_t * arm11, uint8_t instr, tap_state_t state);
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void arm11_add_debug_SCAN_N (arm11_common_t * arm11, uint8_t chain, tap_state_t state);
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int arm11_add_debug_SCAN_N (arm11_common_t * arm11, uint8_t chain, tap_state_t state);
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void arm11_add_debug_INST (arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state);
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int arm11_read_DSCR (arm11_common_t * arm11, uint32_t *dscr);
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int arm11_write_DSCR (arm11_common_t * arm11, uint32_t dscr);
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enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr);
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void arm11_run_instr_data_prepare (arm11_common_t * arm11);
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void arm11_run_instr_data_finish (arm11_common_t * arm11);
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int arm11_run_instr_data_prepare (arm11_common_t * arm11);
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int arm11_run_instr_data_finish (arm11_common_t * arm11);
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int arm11_run_instr_no_data (arm11_common_t * arm11, uint32_t * opcode, size_t count);
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int arm11_run_instr_no_data1 (arm11_common_t * arm11, uint32_t opcode);
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int arm11_run_instr_data_to_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
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@ -263,7 +263,7 @@ int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, uint32_t opcode
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int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
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int arm11_run_instr_data_from_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
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int arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t * data);
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void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
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int arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
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int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
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int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
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@ -161,7 +161,7 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value)
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* \remarks This adds to the JTAG command queue but does \em not execute it.
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*/
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void arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
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int arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
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{
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JTAG_DEBUG("SCREG <= 0x%02x", chain);
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@ -177,6 +177,8 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t s
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jtag_execute_queue_noclear();
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arm11_in_handler_SCAN_N(tmp);
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return jtag_execute_queue();
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}
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/** Write an instruction into the ITR register
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@ -220,7 +222,10 @@ void arm11_add_debug_INST(arm11_common_t * arm11, uint32_t inst, uint8_t * flag,
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*/
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int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
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{
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arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
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int retval;
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retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
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if (retval != ERROR_OK)
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return retval;
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arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
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@ -254,7 +259,10 @@ int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
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*/
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int arm11_write_DSCR(arm11_common_t * arm11, uint32_t dscr)
|
||||
{
|
||||
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
|
||||
int retval;
|
||||
retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
|
||||
|
||||
|
|
@ -331,9 +339,9 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr)
|
|||
* \param arm11 Target state variable.
|
||||
*
|
||||
*/
|
||||
void arm11_run_instr_data_prepare(arm11_common_t * arm11)
|
||||
int arm11_run_instr_data_prepare(arm11_common_t * arm11)
|
||||
{
|
||||
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
|
||||
return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
|
||||
}
|
||||
|
||||
/** Cleanup after ITR/DTR operations
|
||||
|
|
@ -350,9 +358,9 @@ void arm11_run_instr_data_prepare(arm11_common_t * arm11)
|
|||
* \param arm11 Target state variable.
|
||||
*
|
||||
*/
|
||||
void arm11_run_instr_data_finish(arm11_common_t * arm11)
|
||||
int arm11_run_instr_data_finish(arm11_common_t * arm11)
|
||||
{
|
||||
arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
|
||||
return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -757,12 +765,19 @@ int arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcod
|
|||
* \param data Data word that will be written to r0 before \p opcode is executed
|
||||
*
|
||||
*/
|
||||
void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
|
||||
int arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
|
||||
{
|
||||
int retval;
|
||||
/* MRC p14,0,r0,c0,c5,0 */
|
||||
arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
|
||||
retval = arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
arm11_run_instr_no_data1(arm11, opcode);
|
||||
retval = arm11_run_instr_no_data1(arm11, opcode);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/** Apply reads and writes to scan chain 7
|
||||
|
|
@ -776,7 +791,11 @@ void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode
|
|||
*/
|
||||
int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
|
||||
{
|
||||
arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
|
||||
int retval;
|
||||
|
||||
retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue