Correctly parse dmcontrol.
Change-Id: Ibae425f4ccbe9e504c41e185f264f667e091fca4__archive__
parent
8af4a9a053
commit
8cac7d0cee
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@ -20,6 +20,7 @@
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#include "breakpoints.h"
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#include "helper/time_support.h"
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#include "riscv.h"
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#include "debug_defines.h"
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/**
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* Since almost everything can be accomplish by scanning the dbus register, all
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@ -88,12 +89,6 @@
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/*** JTAG registers. ***/
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#define DTMCONTROL 0x10
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#define DTMCONTROL_DBUS_RESET (1<<16)
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#define DTMCONTROL_IDLE (7<<10)
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#define DTMCONTROL_ADDRBITS (0xf<<4)
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#define DTMCONTROL_VERSION (0xf)
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#define DBUS 0x11
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#define DBUS_OP_START 0
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#define DBUS_OP_SIZE 2
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@ -136,20 +131,6 @@ typedef enum slot {
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#define DMCONTROL_NDRESET (1<<1)
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#define DMCONTROL_FULLRESET 1
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#define DMINFO 0x11
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#define DMINFO_ABUSSIZE (0x7fU<<25)
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#define DMINFO_SERIALCOUNT (0xf<<21)
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#define DMINFO_ACCESS128 (1<<20)
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#define DMINFO_ACCESS64 (1<<19)
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#define DMINFO_ACCESS32 (1<<18)
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#define DMINFO_ACCESS16 (1<<17)
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#define DMINFO_ACCESS8 (1<<16)
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#define DMINFO_DRAMSIZE (0x3f<<10)
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#define DMINFO_AUTHENTICATED (1<<5)
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#define DMINFO_AUTHBUSY (1<<4)
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#define DMINFO_AUTHTYPE (3<<2)
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#define DMINFO_VERSION 3
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/*** Info about the core being debugged. ***/
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#define DBUS_ADDRESS_UNKNOWN 0xffff
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@ -192,7 +173,7 @@ typedef struct {
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/* Number of address bits in the dbus register. */
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uint8_t addrbits;
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/* Number of words in Debug RAM. */
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unsigned int dramsize;
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unsigned int dramsize; // TODO: remove
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uint64_t dcsr;
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uint64_t dpc;
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uint64_t misa;
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@ -366,7 +347,7 @@ static void increase_dbus_busy_delay(struct target *target)
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info->dtmcontrol_idle, info->dbus_busy_delay,
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info->interrupt_high_delay);
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dtmcontrol_scan(target, DTMCONTROL_DBUS_RESET);
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dtmcontrol_scan(target, DTM_DTMCONTROL_DBUSRESET);
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}
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static void increase_interrupt_high_delay(struct target *target)
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@ -493,7 +474,7 @@ static uint64_t dbus_read(struct target *target, uint16_t address)
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if (status == DBUS_STATUS_BUSY) {
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increase_dbus_busy_delay(target);
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}
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} while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
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} while (((status != DBUS_STATUS_SUCCESS) || (address_in != address)) &&
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i++ < 256);
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if (status != DBUS_STATUS_SUCCESS) {
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@ -1795,22 +1776,24 @@ static int examine(struct target *target)
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uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
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LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
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LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
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LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
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LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
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LOG_DEBUG(" dbusreset=%d", get_field(dtmcontrol, DTM_DTMCONTROL_DBUSRESET));
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LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTM_DTMCONTROL_IDLE));
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LOG_DEBUG(" dbusstat=%d", get_field(dtmcontrol, DTM_DTMCONTROL_DBUSSTAT));
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LOG_DEBUG(" abits=%d", get_field(dtmcontrol, DTM_DTMCONTROL_ABITS));
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LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTM_DTMCONTROL_VERSION));
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if (dtmcontrol == 0) {
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LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
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return ERROR_FAIL;
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}
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if (get_field(dtmcontrol, DTMCONTROL_VERSION) != 1) {
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if (get_field(dtmcontrol, DTM_DTMCONTROL_VERSION) != 1) {
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LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
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get_field(dtmcontrol, DTMCONTROL_VERSION), dtmcontrol);
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get_field(dtmcontrol, DTM_DTMCONTROL_VERSION), dtmcontrol);
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return ERROR_FAIL;
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}
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riscv013_info_t *info = get_info(target);
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info->addrbits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS);
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info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE);
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info->addrbits = get_field(dtmcontrol, DTM_DTMCONTROL_ABITS);
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info->dtmcontrol_idle = get_field(dtmcontrol, DTM_DTMCONTROL_IDLE);
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if (info->dtmcontrol_idle == 0) {
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// Some old SiFive cores don't set idle but need it to be 1.
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uint32_t idcode = idcode_scan(target);
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@ -1818,32 +1801,27 @@ static int examine(struct target *target)
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info->dtmcontrol_idle = 1;
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}
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uint32_t dminfo = dbus_read(target, DMINFO);
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LOG_DEBUG("dminfo: 0x%08x", dminfo);
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LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
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LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
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LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
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LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
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LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
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LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
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LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
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LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
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LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
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LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
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LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
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LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
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uint32_t dmcontrol = dbus_read(target, DMI_DMCONTROL);
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LOG_DEBUG("dmcontrol: 0x%08x", dmcontrol);
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LOG_DEBUG(" halt=%d", get_field(dmcontrol, DMI_DMCONTROL_HALT));
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LOG_DEBUG(" reset=%d", get_field(dmcontrol, DMI_DMCONTROL_RESET));
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LOG_DEBUG(" dmactive=%d", get_field(dmcontrol, DMI_DMCONTROL_DMACTIVE));
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LOG_DEBUG(" hartid=0x%x", get_field(dmcontrol, DMI_DMCONTROL_HARTID));
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LOG_DEBUG(" haltsum=%d", get_field(dmcontrol, DMI_DMCONTROL_HALTSUM));
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LOG_DEBUG(" authenticated=%d", get_field(dmcontrol, DMI_DMCONTROL_AUTHENTICATED));
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LOG_DEBUG(" authbusy=%d", get_field(dmcontrol, DMI_DMCONTROL_AUTHBUSY));
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LOG_DEBUG(" authtype=%d", get_field(dmcontrol, DMI_DMCONTROL_AUTHTYPE));
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LOG_DEBUG(" version=%d", get_field(dmcontrol, DMI_DMCONTROL_VERSION));
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if (get_field(dminfo, DMINFO_VERSION) != 1) {
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if (get_field(dmcontrol, DMI_DMCONTROL_VERSION) != 1) {
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LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
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"(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
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"(dmcontrol=0x%x)", get_field(dmcontrol, DMI_DMCONTROL_VERSION), dmcontrol);
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return ERROR_FAIL;
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}
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info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
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if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
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if (!get_field(dmcontrol, DMI_DMCONTROL_AUTHENTICATED)) {
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LOG_ERROR("Authentication required by RISC-V core but not "
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"supported by OpenOCD. dminfo=0x%x", dminfo);
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"supported by OpenOCD. dmcontrol=0x%x", dmcontrol);
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return ERROR_FAIL;
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}
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