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arm_adi_v5: Change mem_ap calls to take pointer to AP and not DAP 

Change-Id: I8d3e42056aa5828cb917ca578a54b7d53846a150
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3149
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
__archive__
Andreas Fritiofson 2015-12-06 11:20:49 +01:00
parent f9dfbf3ac7
commit 8a069b7b90
6 changed files with 224 additions and 267 deletions
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7
src/flash/nor/at91sam4l.c
View File

@ -648,7 +648,6 @@ COMMAND_HANDLER(sam4l_handle_reset_deassert)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval = ERROR_OK;
enum reset_types jtag_reset_config = jtag_get_reset_config();
@ -660,14 +659,14 @@ COMMAND_HANDLER(sam4l_handle_reset_deassert)
* After vectreset SMAP release is not needed however makes no harm
*/
if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
if (retval == ERROR_OK)
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR,
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
/* do not return on error here, releasing SMAP reset is more important */
}
int retval2 = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, SMAP_SCR, SMAP_SCR_HCR);
int retval2 = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, SMAP_SCR, SMAP_SCR_HCR);
if (retval2 != ERROR_OK)
return retval2;

5
src/flash/nor/at91samd.c
View File

@ -988,7 +988,6 @@ COMMAND_HANDLER(samd_handle_reset_deassert)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval = ERROR_OK;
enum reset_types jtag_reset_config = jtag_get_reset_config();
@ -1000,9 +999,9 @@ COMMAND_HANDLER(samd_handle_reset_deassert)
* After vectreset DSU release is not needed however makes no harm
*/
if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
if (retval == ERROR_OK)
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR,
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
/* do not return on error here, releasing DSU reset is more important */
}

162
src/target/arm_adi_v5.c
View File

@ -186,7 +186,7 @@ int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
static int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
static int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
uint32_t *value)
{
int retval;
@ -194,12 +194,12 @@ static int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when reading several consecutive addresses.
*/
retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
retval = dap_setup_accessport(ap->dap, CSW_32BIT | CSW_ADDRINC_OFF,
address & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
return dap_queue_ap_read(dap, MEM_AP_REG_BD0 | (address & 0xC), value);
return dap_queue_ap_read(ap->dap, MEM_AP_REG_BD0 | (address & 0xC), value);
}
/**
@ -214,16 +214,16 @@ static int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
* @return ERROR_OK for success; *value holds the result.
* Otherwise a fault code.
*/
static int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
static int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
uint32_t *value)
{
int retval;
retval = mem_ap_read_u32(dap, address, value);
retval = mem_ap_read_u32(ap, address, value);
if (retval != ERROR_OK)
return retval;
return dap_run(dap);
return dap_run(ap->dap);
}
/**
@ -237,7 +237,7 @@ static int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
static int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
static int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
uint32_t value)
{
int retval;
@ -245,12 +245,12 @@ static int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when writing several consecutive addresses.
*/
retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
retval = dap_setup_accessport(ap->dap, CSW_32BIT | CSW_ADDRINC_OFF,
address & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
return dap_queue_ap_write(dap, MEM_AP_REG_BD0 | (address & 0xC),
return dap_queue_ap_write(ap->dap, MEM_AP_REG_BD0 | (address & 0xC),
value);
}
@ -265,15 +265,15 @@ static int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
*
* @return ERROR_OK for success; the data was written. Otherwise a fault code.
*/
static int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
static int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
uint32_t value)
{
int retval = mem_ap_write_u32(dap, address, value);
int retval = mem_ap_write_u32(ap, address, value);
if (retval != ERROR_OK)
return retval;
return dap_run(dap);
return dap_run(ap->dap);
}
/**
@ -288,10 +288,10 @@ static int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
* should normally be true, except when writing to e.g. a FIFO.
* @return ERROR_OK on success, otherwise an error code.
*/
static int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
uint32_t address, bool addrinc)
{
struct adiv5_ap *ap = &dap->ap[dap_ap_get_select(dap)];
struct adiv5_dap *dap = ap->dap;
size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
@ -419,10 +419,10 @@ static int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t s
* should normally be true, except when reading from e.g. a FIFO.
* @return ERROR_OK on success, otherwise an error code.
*/
static int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
uint32_t adr, bool addrinc)
{
struct adiv5_ap *ap = &dap->ap[dap_ap_get_select(dap)];
struct adiv5_dap *dap = ap->dap;
size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
@ -561,60 +561,60 @@ static int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, ui
/*--------------------------------------------------------------------*/
/* Wrapping function with selection of AP */
/*--------------------------------------------------------------------*/
int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_read_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value)
{
dap_ap_select(swjdp, ap);
return mem_ap_read_u32(swjdp, address, value);
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_read_u32(ap, address, value);
}
int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_write_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value)
{
dap_ap_select(swjdp, ap);
return mem_ap_write_u32(swjdp, address, value);
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_write_u32(ap, address, value);
}
int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_read_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value)
{
dap_ap_select(swjdp, ap);
return mem_ap_read_atomic_u32(swjdp, address, value);
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_read_atomic_u32(ap, address, value);
}
int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_write_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value)
{
dap_ap_select(swjdp, ap);
return mem_ap_write_atomic_u32(swjdp, address, value);
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_write_atomic_u32(ap, address, value);
}
int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_read_buf(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
{
dap_ap_select(swjdp, ap);
return mem_ap_read(swjdp, buffer, size, count, address, true);
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_read(ap, buffer, size, count, address, true);
}
int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_write_buf(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
{
dap_ap_select(swjdp, ap);
return mem_ap_write(swjdp, buffer, size, count, address, true);
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_write(ap, buffer, size, count, address, true);
}
int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_read_buf_noincr(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
{
dap_ap_select(swjdp, ap);
return mem_ap_read(swjdp, buffer, size, count, address, false);
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_read(ap, buffer, size, count, address, false);
}
int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_write_buf_noincr(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
{
dap_ap_select(swjdp, ap);
return mem_ap_write(swjdp, buffer, size, count, address, false);
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_write(ap, buffer, size, count, address, false);
}
/*--------------------------------------------------------------------------*/
@ -660,12 +660,12 @@ struct adiv5_dap *dap_init(void)
* in layering. (JTAG is useful without any debug target; but not SWD.)
* And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
*/
int ahbap_debugport_init(struct adiv5_dap *dap, uint8_t apsel)
int ahbap_debugport_init(struct adiv5_ap *ap)
{
/* check that we support packed transfers */
uint32_t csw, cfg;
int retval;
struct adiv5_ap *ap = &dap->ap[apsel];
struct adiv5_dap *dap = ap->dap;
LOG_DEBUG(" ");
@ -683,7 +683,7 @@ int ahbap_debugport_init(struct adiv5_dap *dap, uint8_t apsel)
* Presumably we can ignore the possibility of multiple APs.
*/
dap->ap_current = -1;
dap_ap_select(dap, apsel);
dap_ap_select(dap, ap->ap_num);
dap->last_read = NULL;
for (size_t i = 0; i < 10; i++) {
@ -858,18 +858,15 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_a
return ERROR_FAIL;
}
int dap_get_debugbase(struct adiv5_dap *dap, int ap,
int dap_get_debugbase(struct adiv5_ap *ap,
uint32_t *dbgbase, uint32_t *apid)
{
struct adiv5_dap *dap = ap->dap;
uint32_t ap_old;
int retval;
/* AP address is in bits 31:24 of DP_SELECT */
if (ap >= 256)
return ERROR_COMMAND_SYNTAX_ERROR;
ap_old = dap_ap_get_select(dap);
dap_ap_select(dap, ap);
dap_ap_select(dap, ap->ap_num);
retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
if (retval != ERROR_OK)
@ -886,22 +883,19 @@ int dap_get_debugbase(struct adiv5_dap *dap, int ap,
return ERROR_OK;
}
int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
int dap_lookup_cs_component(struct adiv5_ap *ap,
uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
{
struct adiv5_dap *dap = ap->dap;
uint32_t ap_old;
uint32_t romentry, entry_offset = 0, component_base, devtype;
int retval;
if (ap >= 256)
return ERROR_COMMAND_SYNTAX_ERROR;
*addr = 0;
ap_old = dap_ap_get_select(dap);
dap_ap_select(dap, ap);
do {
retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
@ -911,14 +905,14 @@ int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
if (romentry & 0x1) {
uint32_t c_cid1;
retval = mem_ap_read_atomic_u32(dap, component_base | 0xff4, &c_cid1);
retval = mem_ap_sel_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
if (retval != ERROR_OK) {
LOG_ERROR("Can't read component with base address 0x%" PRIx32
", the corresponding core might be turned off", component_base);
return retval;
}
if (((c_cid1 >> 4) & 0x0f) == 1) {
retval = dap_lookup_cs_component(dap, ap, component_base,
retval = dap_lookup_cs_component(ap, component_base,
type, addr, idx);
if (retval == ERROR_OK)
break;
@ -926,7 +920,7 @@ int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
return retval;
}
retval = mem_ap_read_atomic_u32(dap,
retval = mem_ap_sel_read_atomic_u32(ap,
(component_base & 0xfffff000) | 0xfcc,
&devtype);
if (retval != ERROR_OK)
@ -951,8 +945,9 @@ int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
}
static int dap_rom_display(struct command_context *cmd_ctx,
struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
struct adiv5_ap *ap, uint32_t dbgbase, int depth)
{
struct adiv5_dap *dap = ap->dap;
int retval;
uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
uint16_t entry_offset;
@ -973,19 +968,19 @@ static int dap_rom_display(struct command_context *cmd_ctx,
command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
@ -1007,7 +1002,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
/* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
for (entry_offset = 0; ; entry_offset += 4) {
retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
@ -1022,43 +1017,43 @@ static int dap_rom_display(struct command_context *cmd_ctx,
component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
/* IDs are in last 4K section */
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
if (retval != ERROR_OK) {
command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
", the corresponding core might be turned off", tabs, component_base);
continue;
}
c_pid0 &= 0xff;
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
if (retval != ERROR_OK)
return retval;
c_pid1 &= 0xff;
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
if (retval != ERROR_OK)
return retval;
c_pid2 &= 0xff;
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
if (retval != ERROR_OK)
return retval;
c_pid3 &= 0xff;
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
if (retval != ERROR_OK)
return retval;
c_pid4 &= 0xff;
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
if (retval != ERROR_OK)
return retval;
c_cid0 &= 0xff;
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
if (retval != ERROR_OK)
return retval;
c_cid1 &= 0xff;
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
if (retval != ERROR_OK)
return retval;
c_cid2 &= 0xff;
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
if (retval != ERROR_OK)
return retval;
c_cid3 &= 0xff;
@ -1078,7 +1073,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
unsigned minor;
const char *major = "Reserved", *subtype = "Reserved";
retval = mem_ap_read_atomic_u32(dap,
retval = mem_ap_sel_read_atomic_u32(ap,
(component_base & 0xfffff000) | 0xfcc,
&devtype);
if (retval != ERROR_OK)
@ -1404,7 +1399,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
/* ROM Table? */
if (((c_cid1 >> 4) & 0x0f) == 1) {
retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
if (retval != ERROR_OK)
return retval;
}
@ -1420,20 +1415,21 @@ static int dap_rom_display(struct command_context *cmd_ctx,
}
static int dap_info_command(struct command_context *cmd_ctx,
struct adiv5_dap *dap, int ap)
struct adiv5_ap *ap)
{
struct adiv5_dap *dap = ap->dap;
int retval;
uint32_t dbgbase, apid;
int romtable_present = 0;
uint8_t mem_ap;
uint32_t ap_old;
retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
retval = dap_get_debugbase(ap, &dbgbase, &apid);
if (retval != ERROR_OK)
return retval;
ap_old = dap_ap_get_select(dap);
dap_ap_select(dap, ap);
dap_ap_select(dap, ap->ap_num);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
@ -1460,11 +1456,11 @@ static int dap_info_command(struct command_context *cmd_ctx,
if (mem_ap)
command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
} else
command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
if (romtable_present)
dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
dap_rom_display(cmd_ctx, ap, dbgbase, 0);
else
command_print(cmd_ctx, "\tNo ROM table present");
dap_ap_select(dap, ap_old);
@ -1485,12 +1481,14 @@ COMMAND_HANDLER(handle_dap_info_command)
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
if (apsel >= 256)
return ERROR_COMMAND_SYNTAX_ERROR;
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
return dap_info_command(CMD_CTX, dap, apsel);
return dap_info_command(CMD_CTX, &dap->ap[apsel]);
}
COMMAND_HANDLER(dap_baseaddr_command)

22
src/target/arm_adi_v5.h
View File

@ -443,38 +443,38 @@ int dap_setup_accessport(struct adiv5_dap *swjdp,
uint32_t csw, uint32_t tar);
/* Queued MEM-AP memory mapped single word transfers with selection of ap */
int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_read_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value);
int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_write_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value);
/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_read_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value);
int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_write_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value);
/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_read_buf(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_write_buf(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
/* Synchronous, non-incrementing buffer functions for accessing fifos, with
* selection of ap */
int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_read_buf_noincr(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
int mem_ap_sel_write_buf_noincr(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
/* Create DAP struct */
struct adiv5_dap *dap_init(void);
/* Initialisation of the debug system, power domains and registers */
int ahbap_debugport_init(struct adiv5_dap *swjdp, uint8_t apsel);
int ahbap_debugport_init(struct adiv5_ap *ap);
/* Probe the AP for ROM Table location */
int dap_get_debugbase(struct adiv5_dap *dap, int ap,
int dap_get_debugbase(struct adiv5_ap *ap,
uint32_t *dbgbase, uint32_t *apid);
/* Probe Access Ports to find a particular type */
@ -483,7 +483,7 @@ int dap_find_ap(struct adiv5_dap *dap,
struct adiv5_ap **ap_out);
/* Lookup CoreSight component */
int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
int dap_lookup_cs_component(struct adiv5_ap *ap,
uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
struct target;

171
src/target/cortex_a.c
View File

@ -188,18 +188,17 @@ static int cortex_a_mmu_modify(struct target *target, int enable)
static int cortex_a8_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
LOG_DEBUG(" ");
/* Unlocking the debug registers for modification
* The debugport might be uninitialised so try twice */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval != ERROR_OK) {
/* try again */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval == ERROR_OK)
LOG_USER(
@ -215,7 +214,6 @@ static int cortex_a8_init_debug_access(struct target *target)
static int cortex_a_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
uint32_t dbg_osreg;
uint32_t cortex_part_num;
@ -228,7 +226,7 @@ static int cortex_a_init_debug_access(struct target *target)
switch (cortex_part_num) {
case CORTEX_A7_PARTNUM:
case CORTEX_A15_PARTNUM:
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLSR,
&dbg_osreg);
if (retval != ERROR_OK)
@ -238,7 +236,7 @@ static int cortex_a_init_debug_access(struct target *target)
if (dbg_osreg & CPUDBG_OSLAR_LK_MASK)
/* Unlocking the DEBUG OS registers for modification */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
break;
@ -254,7 +252,7 @@ static int cortex_a_init_debug_access(struct target *target)
return retval;
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
@ -262,13 +260,13 @@ static int cortex_a_init_debug_access(struct target *target)
return retval;
/* Disable cacheline fills and force cache write-through in debug state */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCCR, 0);
if (retval != ERROR_OK)
return retval;
/* Disable TLB lookup and refill/eviction in debug state */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSMCR, 0);
if (retval != ERROR_OK)
return retval;
@ -287,11 +285,10 @@ static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool f
* Writes final value of DSCR into *dscr. Pass force to force always
* reading DSCR at least once. */
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
long long then = timeval_ms();
while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
force = false;
int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
int retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK) {
LOG_ERROR("Could not read DSCR register");
@ -316,7 +313,6 @@ static int cortex_a_exec_opcode(struct target *target,
uint32_t dscr;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
dscr = dscr_p ? *dscr_p : 0;
@ -327,14 +323,14 @@ static int cortex_a_exec_opcode(struct target *target,
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, opcode);
if (retval != ERROR_OK)
return retval;
long long then = timeval_ms();
do {
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK) {
LOG_ERROR("Could not read DSCR register");
@ -361,7 +357,6 @@ static int cortex_a_read_regs_through_mem(struct target *target, uint32_t addres
{
int retval = ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
retval = cortex_a_dap_read_coreregister_u32(target, regfile, 0);
if (retval != ERROR_OK)
@ -373,7 +368,7 @@ static int cortex_a_read_regs_through_mem(struct target *target, uint32_t addres
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap->ap_num,
retval = mem_ap_sel_read_buf(armv7a->memory_ap,
(uint8_t *)(&regfile[1]), 4, 15, address);
return retval;
@ -386,7 +381,6 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
uint8_t reg = regnum&0xFF;
uint32_t dscr = 0;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
if (reg > 17)
return retval;
@ -425,7 +419,7 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
/* Wait for DTRRXfull then read DTRRTX */
long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -435,7 +429,7 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
}
}
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, value);
LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
@ -449,12 +443,11 @@ static int cortex_a_dap_write_coreregister_u32(struct target *target,
uint8_t Rd = regnum&0xFF;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -472,7 +465,7 @@ static int cortex_a_dap_write_coreregister_u32(struct target *target,
/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
LOG_DEBUG("write DCC 0x%08" PRIx32, value);
retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, value);
if (retval != ERROR_OK)
return retval;
@ -528,9 +521,8 @@ static int cortex_a_dap_write_memap_register_u32(struct target *target,
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num, address, value);
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap, address, value);
return retval;
}
@ -554,14 +546,13 @@ static inline struct cortex_a_common *dpm_to_a(struct arm_dpm *dpm)
static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
return mem_ap_sel_write_u32(a->armv7a_common.arm.dap,
a->armv7a_common.debug_ap->ap_num, a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
return mem_ap_sel_write_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
uint32_t *dscr_p)
{
struct adiv5_dap *swjdp = a->armv7a_common.arm.dap;
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
@ -571,7 +562,7 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
/* Wait for DTRRXfull */
long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
@ -582,7 +573,7 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
}
}
retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
@ -597,14 +588,13 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
{
struct cortex_a_common *a = dpm_to_a(dpm);
struct adiv5_dap *swjdp = a->armv7a_common.arm.dap;
uint32_t dscr;
int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */
long long then = timeval_ms();
for (;; ) {
retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
@ -878,7 +868,6 @@ static int cortex_a_poll(struct target *target)
uint32_t dscr;
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = &cortex_a->armv7a_common;
struct adiv5_dap *swjdp = armv7a->arm.dap;
enum target_state prev_target_state = target->state;
/* toggle to another core is done by gdb as follow */
/* maint packet J core_id */
@ -892,7 +881,7 @@ static int cortex_a_poll(struct target *target)
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return retval;
}
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -948,13 +937,12 @@ static int cortex_a_halt(struct target *target)
int retval = ERROR_OK;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
/*
* Tell the core to be halted by writing DRCR with 0x1
* and then wait for the core to be halted.
*/
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
if (retval != ERROR_OK)
return retval;
@ -962,19 +950,19 @@ static int cortex_a_halt(struct target *target)
/*
* enter halting debug mode
*/
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
if (retval != ERROR_OK)
return retval;
long long then = timeval_ms();
for (;; ) {
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -1089,7 +1077,6 @@ static int cortex_a_internal_restart(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
struct adiv5_dap *swjdp = arm->dap;
int retval;
uint32_t dscr;
/*
@ -1100,7 +1087,7 @@ static int cortex_a_internal_restart(struct target *target)
* disable IRQs by default, with optional override...
*/
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -1108,12 +1095,12 @@ static int cortex_a_internal_restart(struct target *target)
if ((dscr & DSCR_INSTR_COMP) == 0)
LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
@ -1121,7 +1108,7 @@ static int cortex_a_internal_restart(struct target *target)
long long then = timeval_ms();
for (;; ) {
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -1207,13 +1194,12 @@ static int cortex_a_debug_entry(struct target *target)
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
struct adiv5_dap *swjdp = armv7a->arm.dap;
struct reg *reg;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
/* REVISIT surely we should not re-read DSCR !! */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -1225,7 +1211,7 @@ static int cortex_a_debug_entry(struct target *target)
/* Enable the ITR execution once we are in debug mode */
dscr |= DSCR_ITR_EN;
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK)
return retval;
@ -1237,7 +1223,7 @@ static int cortex_a_debug_entry(struct target *target)
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
uint32_t wfar;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_WFAR,
&wfar);
if (retval != ERROR_OK)
@ -1356,11 +1342,10 @@ static int cortex_a_post_debug_entry(struct target *target)
int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
uint32_t dscr;
/* Read DSCR */
int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
int retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (ERROR_OK != retval)
return retval;
@ -1371,7 +1356,7 @@ int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsign
dscr |= value & bit_mask;
/* write new DSCR */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
return retval;
}
@ -1952,8 +1937,8 @@ static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t
uint32_t new_dscr = (*dscr & ~DSCR_EXT_DCC_MASK) | mode;
if (new_dscr != *dscr) {
struct armv7a_common *armv7a = target_to_armv7a(target);
int retval = mem_ap_sel_write_atomic_u32(armv7a->arm.dap,
armv7a->debug_ap->ap_num, armv7a->debug_base + CPUDBG_DSCR, new_dscr);
int retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, new_dscr);
if (retval == ERROR_OK)
*dscr = new_dscr;
return retval;
@ -1967,12 +1952,11 @@ static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
{
/* Waits until the specified bit(s) of DSCR take on a specified value. */
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
long long then = timeval_ms();
int retval;
while ((*dscr & mask) != value) {
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK)
return retval;
@ -1989,7 +1973,6 @@ static int cortex_a_read_copro(struct target *target, uint32_t opcode,
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
/* Move from coprocessor to R0. */
retval = cortex_a_exec_opcode(target, opcode, dscr);
@ -2011,7 +1994,7 @@ static int cortex_a_read_copro(struct target *target, uint32_t opcode,
return retval;
/* Read the value transferred to DTRTX. */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
@ -2044,10 +2027,9 @@ static int cortex_a_write_copro(struct target *target, uint32_t opcode,
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
/* Write the value into DTRRX. */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, data);
if (retval != ERROR_OK)
return retval;
@ -2129,7 +2111,6 @@ static int cortex_a_write_apb_ab_memory_slow(struct target *target,
* - R0 is marked dirty.
*/
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
struct arm *arm = &armv7a->arm;
int retval;
@ -2151,7 +2132,7 @@ static int cortex_a_write_apb_ab_memory_slow(struct target *target,
data = target_buffer_get_u16(target, buffer);
else
data = target_buffer_get_u32(target, buffer);
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, data);
if (retval != ERROR_OK)
return retval;
@ -2203,7 +2184,6 @@ static int cortex_a_write_apb_ab_memory_fast(struct target *target,
* - R0 is marked dirty.
*/
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
/* Switch to fast mode if not already in that mode. */
@ -2212,13 +2192,13 @@ static int cortex_a_write_apb_ab_memory_fast(struct target *target,
return retval;
/* Latch STC instruction. */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
if (retval != ERROR_OK)
return retval;
/* Transfer all the data and issue all the instructions. */
return mem_ap_sel_write_buf_noincr(swjdp, armv7a->debug_ap->ap_num, buffer,
return mem_ap_sel_write_buf_noincr(armv7a->debug_ap, buffer,
4, count, armv7a->debug_base + CPUDBG_DTRRX);
}
@ -2229,7 +2209,6 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
/* Write memory through APB-AP. */
int retval, final_retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
struct arm *arm = &armv7a->arm;
uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
@ -2244,13 +2223,13 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
return ERROR_OK;
/* Clear any abort. */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
/* Read DSCR. */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -2269,7 +2248,7 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
goto out;
/* Get the memory address into R0. */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, address);
if (retval != ERROR_OK)
goto out;
@ -2313,7 +2292,7 @@ out:
/* If there were any sticky abort flags, clear them. */
if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
fault_dscr = dscr;
mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
} else {
@ -2347,7 +2326,7 @@ out:
/* If the DCC is nonempty, clear it. */
if (dscr & DSCR_DTRTX_FULL_LATCHED) {
uint32_t dummy;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &dummy);
if (final_retval == ERROR_OK)
final_retval = retval;
@ -2375,7 +2354,6 @@ static int cortex_a_read_apb_ab_memory_slow(struct target *target,
* - R0 is marked dirty.
*/
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
struct arm *arm = &armv7a->arm;
int retval;
@ -2420,7 +2398,7 @@ static int cortex_a_read_apb_ab_memory_slow(struct target *target,
return retval;
/* Read the value transferred to DTRTX into the buffer. */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &data);
if (retval != ERROR_OK)
return retval;
@ -2450,7 +2428,6 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
* - R0 is marked dirty.
*/
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
uint32_t u32;
int retval;
@ -2473,7 +2450,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
return retval;
/* Latch LDC instruction. */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
if (retval != ERROR_OK)
return retval;
@ -2484,7 +2461,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
* memory. The last read of DTRTX in this call reads the second-to-last
* word from memory and issues the read instruction for the last word.
*/
retval = mem_ap_sel_read_buf_noincr(swjdp, armv7a->debug_ap->ap_num, buffer,
retval = mem_ap_sel_read_buf_noincr(armv7a->debug_ap, buffer,
4, count, armv7a->debug_base + CPUDBG_DTRTX);
if (retval != ERROR_OK)
return retval;
@ -2518,7 +2495,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
/* Read the value transferred to DTRTX into the buffer. This is the last
* word. */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &u32);
if (retval != ERROR_OK)
return retval;
@ -2534,7 +2511,6 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
/* Read memory through APB-AP. */
int retval, final_retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
struct arm *arm = &armv7a->arm;
uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
@ -2549,13 +2525,13 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
return ERROR_OK;
/* Clear any abort. */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
/* Read DSCR */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -2574,7 +2550,7 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
goto out;
/* Get the memory address into R0. */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, address);
if (retval != ERROR_OK)
goto out;
@ -2606,7 +2582,7 @@ out:
/* If there were any sticky abort flags, clear them. */
if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
fault_dscr = dscr;
mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
} else {
@ -2640,7 +2616,7 @@ out:
/* If the DCC is nonempty, clear it. */
if (dscr & DSCR_DTRTX_FULL_LATCHED) {
uint32_t dummy;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &dummy);
if (final_retval == ERROR_OK)
final_retval = retval;
@ -2735,7 +2711,7 @@ static int cortex_a_read_memory_ahb(struct target *target, uint32_t address,
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap->ap_num, buffer, size, count, address);
retval = mem_ap_sel_read_buf(armv7a->memory_ap, buffer, size, count, address);
return retval;
}
@ -2816,7 +2792,7 @@ static int cortex_a_write_memory_ahb(struct target *target, uint32_t address,
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
retval = mem_ap_sel_write_buf(swjdp, armv7a->memory_ap->ap_num, buffer, size, count, address);
retval = mem_ap_sel_write_buf(armv7a->memory_ap, buffer, size, count, address);
return retval;
}
@ -2893,7 +2869,6 @@ static int cortex_a_handle_target_request(void *priv)
{
struct target *target = priv;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
if (!target_was_examined(target))
@ -2904,16 +2879,16 @@ static int cortex_a_handle_target_request(void *priv)
if (target->state == TARGET_RUNNING) {
uint32_t request;
uint32_t dscr;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
/* check if we have data */
while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &request);
if (retval == ERROR_OK) {
target_request(target, request);
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
}
}
@ -2945,7 +2920,7 @@ static int cortex_a_examine_first(struct target *target)
/* We do one extra read to ensure DAP is configured,
* we call ahbap_debugport_init(swjdp) instead
*/
retval = ahbap_debugport_init(swjdp, armv7a->debug_ap->ap_num);
retval = ahbap_debugport_init(armv7a->debug_ap);
if (retval != ERROR_OK)
return retval;
@ -2967,11 +2942,11 @@ static int cortex_a_examine_first(struct target *target)
int32_t coreidx = target->coreid;
LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
target->cmd_name);
retval = dap_get_debugbase(swjdp, armv7a->debug_ap->ap_num, &dbgbase, &apid);
retval = dap_get_debugbase(armv7a->debug_ap, &dbgbase, &apid);
if (retval != ERROR_OK)
return retval;
/* Lookup 0x15 -- Processor DAP */
retval = dap_lookup_cs_component(swjdp, armv7a->debug_ap->ap_num, dbgbase, 0x15,
retval = dap_lookup_cs_component(armv7a->debug_ap, dbgbase, 0x15,
&armv7a->debug_base, &coreidx);
if (retval != ERROR_OK) {
LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
@ -2983,33 +2958,33 @@ static int cortex_a_examine_first(struct target *target)
} else
armv7a->debug_base = target->dbgbase;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_CPUID, &cpuid);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_CPUID, &cpuid);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "CPUID");
return retval;
}
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_CTYPR, &ctypr);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "CTYPR");
return retval;
}
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_TTYPR, &ttypr);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "TTYPR");
return retval;
}
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DIDR, &didr);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "DIDR");
@ -3030,7 +3005,7 @@ static int cortex_a_examine_first(struct target *target)
if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
CORTEX_A15_PARTNUM) {
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
@ -3042,7 +3017,7 @@ static int cortex_a_examine_first(struct target *target)
if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
CORTEX_A7_PARTNUM) {
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
@ -3050,7 +3025,7 @@ static int cortex_a_examine_first(struct target *target)
return retval;
}
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
if (retval != ERROR_OK)

124
src/target/cortex_m.c
View File

@ -67,23 +67,22 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
uint32_t dcrdr;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
if (target->dbg_msg_enabled) {
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, &dcrdr);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRSR, regnum);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, value);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
@ -91,7 +90,7 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
/* restore DCB_DCRDR - this needs to be in a separate
* transaction otherwise the emulated DCC channel breaks */
if (retval == ERROR_OK)
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, dcrdr);
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
}
return retval;
@ -101,23 +100,22 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
uint32_t dcrdr;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
if (target->dbg_msg_enabled) {
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, &dcrdr);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, value);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRSR, regnum | DCRSR_WnR);
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
@ -125,7 +123,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
if (retval == ERROR_OK)
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, dcrdr);
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
}
return retval;
@ -136,33 +134,31 @@ static int cortex_m_write_debug_halt_mask(struct target *target,
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
/* mask off status bits */
cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
/* create new register mask */
cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
return mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, cortex_m->dcb_dhcsr);
return mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
}
static int cortex_m_clear_halt(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
int retval;
/* clear step if any */
cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
/* Read Debug Fault Status Register */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_DFSR, &cortex_m->nvic_dfsr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
/* Clear Debug Fault Status */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_DFSR, cortex_m->nvic_dfsr);
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
@ -174,7 +170,6 @@ static int cortex_m_single_step_core(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
uint32_t dhcsr_save;
int retval;
@ -186,12 +181,12 @@ static int cortex_m_single_step_core(struct target *target)
* HALT can put the core into an unknown state.
*/
if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR,
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR,
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
@ -234,22 +229,22 @@ static int cortex_m_endreset_event(struct target *target)
struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
/* REVISIT The four debug monitor bits are currently ignored... */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, &dcb_demcr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
/* this register is used for emulated dcc channel */
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, 0);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
if (retval != ERROR_OK)
return retval;
/* Enable debug requests */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_DEBUGEN);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
@ -264,7 +259,7 @@ static int cortex_m_endreset_event(struct target *target)
* choices *EXCEPT* explicitly scripted overrides like "vector_catch"
* or manual updates to the NVIC SHCSR and CCR registers.
*/
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, TRCENA | armv7m->demcr);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
if (retval != ERROR_OK)
return retval;
@ -310,7 +305,7 @@ static int cortex_m_endreset_event(struct target *target)
register_cache_invalidate(armv7m->arm.core_cache);
/* make sure we have latest dhcsr flags */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
return retval;
}
@ -346,47 +341,47 @@ static int cortex_m_examine_exception_reason(struct target *target)
struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_SHCSR, &shcsr);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
if (retval != ERROR_OK)
return retval;
switch (armv7m->exception_number) {
case 2: /* NMI */
break;
case 3: /* Hard Fault */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_HFSR, &except_sr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
if (except_sr & 0x40000000) {
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_CFSR, &cfsr);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
if (retval != ERROR_OK)
return retval;
}
break;
case 4: /* Memory Management */
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_CFSR, &except_sr);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_MMFAR, &except_ar);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
if (retval != ERROR_OK)
return retval;
break;
case 5: /* Bus Fault */
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_CFSR, &except_sr);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_BFAR, &except_ar);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
if (retval != ERROR_OK)
return retval;
break;
case 6: /* Usage Fault */
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_CFSR, &except_sr);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_DFSR, &except_sr);
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
break;
@ -415,13 +410,12 @@ static int cortex_m_debug_entry(struct target *target)
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct arm *arm = &armv7m->arm;
struct adiv5_dap *swjdp = armv7m->arm.dap;
struct reg *r;
LOG_DEBUG(" ");
cortex_m_clear_halt(target);
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
@ -496,10 +490,9 @@ static int cortex_m_poll(struct target *target)
enum target_state prev_target_state = target->state;
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
/* Read from Debug Halting Control and Status Register */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK) {
target->state = TARGET_UNKNOWN;
return retval;
@ -520,7 +513,7 @@ static int cortex_m_poll(struct target *target)
detected_failure = ERROR_FAIL;
/* refresh status bits */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
}
@ -625,7 +618,6 @@ static int cortex_m_soft_reset_halt(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
@ -636,13 +628,13 @@ static int cortex_m_soft_reset_halt(struct target *target)
LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
/* Enter debug state on reset; restore DEMCR in endreset_event() */
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR,
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
if (retval != ERROR_OK)
return retval;
/* Request a core-only reset */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_AIRCR,
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
AIRCR_VECTKEY | AIRCR_VECTRESET);
if (retval != ERROR_OK)
return retval;
@ -652,9 +644,9 @@ static int cortex_m_soft_reset_halt(struct target *target)
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
while (timeout < 100) {
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &dcb_dhcsr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
if (retval == ERROR_OK) {
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_DFSR,
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
&cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
@ -796,7 +788,6 @@ static int cortex_m_step(struct target *target, int current,
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct adiv5_dap *swjdp = armv7m->arm.dap;
struct breakpoint *breakpoint = NULL;
struct reg *pc = armv7m->arm.pc;
bool bkpt_inst_found = false;
@ -898,7 +889,7 @@ static int cortex_m_step(struct target *target, int current,
/* Wait for pending handlers to complete or timeout */
do {
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num,
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap,
DCB_DHCSR,
&cortex_m->dcb_dhcsr);
if (retval != ERROR_OK) {
@ -933,7 +924,7 @@ static int cortex_m_step(struct target *target, int current,
}
}
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
@ -970,7 +961,6 @@ static int cortex_m_assert_reset(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
LOG_DEBUG("target->state: %s",
@ -1001,11 +991,11 @@ static int cortex_m_assert_reset(struct target *target)
/* Enable debug requests */
int retval;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_DEBUGEN);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
@ -1013,19 +1003,19 @@ static int cortex_m_assert_reset(struct target *target)
/* If the processor is sleeping in a WFI or WFE instruction, the
* C_HALT bit must be asserted to regain control */
if (cortex_m->dcb_dhcsr & S_SLEEP) {
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DCRDR, 0);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
if (retval != ERROR_OK)
return retval;
if (!target->reset_halt) {
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m->dcb_dhcsr & C_MASKINTS) {
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DHCSR,
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_DEBUGEN | C_HALT);
if (retval != ERROR_OK)
return retval;
@ -1043,7 +1033,7 @@ static int cortex_m_assert_reset(struct target *target)
* bad vector table entries. Should this include MMERR or
* other flags too?
*/
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR,
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
if (retval != ERROR_OK)
return retval;
@ -1067,13 +1057,13 @@ static int cortex_m_assert_reset(struct target *target)
"handler to reset any peripherals or configure hardware srst support.");
}
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_AIRCR,
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
if (retval != ERROR_OK)
LOG_DEBUG("Ignoring AP write error right after reset");
retval = ahbap_debugport_init(swjdp, armv7m->debug_ap->ap_num);
retval = ahbap_debugport_init(armv7m->debug_ap);
if (retval != ERROR_OK) {
LOG_ERROR("DP initialisation failed");
return retval;
@ -1085,7 +1075,7 @@ static int cortex_m_assert_reset(struct target *target)
* after reset) on LM3S6918 -- Michael Schwingen
*/
uint32_t tmp;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, NVIC_AIRCR, &tmp);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
if (retval != ERROR_OK)
return retval;
}
@ -1119,7 +1109,7 @@ static int cortex_m_deassert_reset(struct target *target)
if ((jtag_reset_config & RESET_HAS_SRST) &&
!(jtag_reset_config & RESET_SRST_NO_GATING)) {
int retval = ahbap_debugport_init(armv7m->arm.dap, armv7m->debug_ap->ap_num);
int retval = ahbap_debugport_init(armv7m->debug_ap);
if (retval != ERROR_OK) {
LOG_ERROR("DP initialisation failed");
return retval;
@ -1672,7 +1662,6 @@ static int cortex_m_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
if (armv7m->arm.is_armv6m) {
/* armv6m does not handle unaligned memory access */
@ -1680,14 +1669,13 @@ static int cortex_m_read_memory(struct target *target, uint32_t address,
return ERROR_TARGET_UNALIGNED_ACCESS;
}
return mem_ap_sel_read_buf(swjdp, armv7m->debug_ap->ap_num, buffer, size, count, address);
return mem_ap_sel_read_buf(armv7m->debug_ap, buffer, size, count, address);
}
static int cortex_m_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
if (armv7m->arm.is_armv6m) {
/* armv6m does not handle unaligned memory access */
@ -1695,7 +1683,7 @@ static int cortex_m_write_memory(struct target *target, uint32_t address,
return ERROR_TARGET_UNALIGNED_ACCESS;
}
return mem_ap_sel_write_buf(swjdp, armv7m->debug_ap->ap_num, buffer, size, count, address);
return mem_ap_sel_write_buf(armv7m->debug_ap, buffer, size, count, address);
}
static int cortex_m_init_target(struct command_context *cmd_ctx,
@ -1916,7 +1904,7 @@ int cortex_m_examine(struct target *target)
/* stlink shares the examine handler but does not support
* all its calls */
if (!armv7m->stlink) {
retval = ahbap_debugport_init(swjdp, armv7m->debug_ap->ap_num);
retval = ahbap_debugport_init(armv7m->debug_ap);
if (retval != ERROR_OK)
return retval;
}
@ -2027,12 +2015,11 @@ int cortex_m_examine(struct target *target)
static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
uint16_t dcrdr;
uint8_t buf[2];
int retval;
retval = mem_ap_sel_read_buf_noincr(swjdp, armv7m->debug_ap->ap_num, buf, 2, 1, DCB_DCRDR);
retval = mem_ap_sel_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
if (retval != ERROR_OK)
return retval;
@ -2046,7 +2033,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr
* signify we have read data */
if (dcrdr & (1 << 0)) {
target_buffer_set_u16(target, buf, 0);
retval = mem_ap_sel_write_buf_noincr(swjdp, armv7m->debug_ap->ap_num, buf, 2, 1, DCB_DCRDR);
retval = mem_ap_sel_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
if (retval != ERROR_OK)
return retval;
}
@ -2194,7 +2181,6 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
struct target *target = get_current_target(CMD_CTX);
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
struct adiv5_dap *swjdp = armv7m->arm.dap;
uint32_t demcr = 0;
int retval;
@ -2202,7 +2188,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, &demcr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
if (retval != ERROR_OK)
return retval;
@ -2239,10 +2225,10 @@ write:
demcr |= catch;
/* write, but don't assume it stuck (why not??) */
retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, demcr);
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap->ap_num, DCB_DEMCR, &demcr);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
if (retval != ERROR_OK)
return retval;