Merge remote-tracking branch 'origin/riscv' into riscv-compliance
mwachs5
commit
87abbe4a51
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@ -764,10 +764,10 @@ static void cache_set32(struct target *target, unsigned int index, uint32_t data
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if (info->dram_cache[index].valid &&
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info->dram_cache[index].data == data) {
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// This is already preset on the target.
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LOG_DEBUG("cache[0x%x] = 0x%x (hit)", index, data);
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LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
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return;
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}
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LOG_DEBUG("cache[0x%x] = 0x%x", index, data);
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LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
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info->dram_cache[index].data = data;
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info->dram_cache[index].valid = true;
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info->dram_cache[index].dirty = true;
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@ -1033,6 +1033,7 @@ static int wait_for_state(struct target *target, enum target_state state)
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static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
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{
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riscv011_info_t *info = get_info(target);
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cache_set32(target, 0, csrr(S0, csr));
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cache_set_store(target, 1, S0, SLOT0);
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cache_set_jump(target, 2);
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@ -1042,6 +1043,13 @@ static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
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*value = cache_get(target, SLOT0);
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LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
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uint32_t exception = cache_get32(target, info->dramsize-1);
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if (exception) {
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LOG_ERROR("Got exception 0x%x when reading CSR 0x%x", exception, csr);
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*value = ~0;
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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@ -1496,6 +1504,104 @@ static void deinit_target(struct target *target)
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info->version_specific = NULL;
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}
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static int maybe_add_trigger_t1(struct target *target, struct trigger *trigger,
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uint64_t tdata1)
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{
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riscv011_info_t *info = get_info(target);
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const uint32_t bpcontrol_x = 1<<0;
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const uint32_t bpcontrol_w = 1<<1;
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const uint32_t bpcontrol_r = 1<<2;
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const uint32_t bpcontrol_u = 1<<3;
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const uint32_t bpcontrol_s = 1<<4;
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const uint32_t bpcontrol_h = 1<<5;
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const uint32_t bpcontrol_m = 1<<6;
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const uint32_t bpcontrol_bpmatch = 0xf << 7;
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const uint32_t bpcontrol_bpaction = 0xff << 11;
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if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
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// Trigger is already in use, presumably by user code.
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
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tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
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tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
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tdata1 = set_field(tdata1, bpcontrol_u, !!(info->misa & (1 << ('U' - 'A'))));
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tdata1 = set_field(tdata1, bpcontrol_s, !!(info->misa & (1 << ('S' - 'A'))));
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tdata1 = set_field(tdata1, bpcontrol_h, !!(info->misa & (1 << ('H' - 'A'))));
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tdata1 |= bpcontrol_m;
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tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); // exact match
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tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); // cause bp exception
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write_csr(target, CSR_TDATA1, tdata1);
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uint64_t tdata1_rb;
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read_csr(target, &tdata1_rb, CSR_TDATA1);
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LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
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if (tdata1 != tdata1_rb) {
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LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
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PRIx64 " to tdata1 it contains 0x%" PRIx64,
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tdata1, tdata1_rb);
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write_csr(target, CSR_TDATA1, 0);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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write_csr(target, CSR_TDATA2, trigger->address);
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return ERROR_OK;
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}
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static int maybe_add_trigger_t2(struct target *target, struct trigger *trigger,
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uint64_t tdata1)
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{
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riscv011_info_t *info = get_info(target);
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// tselect is already set
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if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
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// Trigger is already in use, presumably by user code.
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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// address/data match trigger
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tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
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tdata1 = set_field(tdata1, MCONTROL_ACTION,
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MCONTROL_ACTION_DEBUG_MODE);
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tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
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tdata1 |= MCONTROL_M;
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if (info->misa & (1 << ('H' - 'A')))
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tdata1 |= MCONTROL_H;
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if (info->misa & (1 << ('S' - 'A')))
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tdata1 |= MCONTROL_S;
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if (info->misa & (1 << ('U' - 'A')))
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tdata1 |= MCONTROL_U;
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if (trigger->execute)
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tdata1 |= MCONTROL_EXECUTE;
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if (trigger->read)
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tdata1 |= MCONTROL_LOAD;
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if (trigger->write)
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tdata1 |= MCONTROL_STORE;
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write_csr(target, CSR_TDATA1, tdata1);
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uint64_t tdata1_rb;
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read_csr(target, &tdata1_rb, CSR_TDATA1);
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LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
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if (tdata1 != tdata1_rb) {
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LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
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PRIx64 " to tdata1 it contains 0x%" PRIx64,
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tdata1, tdata1_rb);
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write_csr(target, CSR_TDATA1, 0);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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write_csr(target, CSR_TDATA2, trigger->address);
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return ERROR_OK;
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}
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static int add_trigger(struct target *target, struct trigger *trigger)
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{
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riscv011_info_t *info = get_info(target);
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@ -1514,51 +1620,23 @@ static int add_trigger(struct target *target, struct trigger *trigger)
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read_csr(target, &tdata1, CSR_TDATA1);
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int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
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if (type != 2) {
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continue;
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int result;
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switch (type) {
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case 1:
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result = maybe_add_trigger_t1(target, trigger, tdata1);
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break;
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case 2:
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result = maybe_add_trigger_t2(target, trigger, tdata1);
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break;
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default:
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LOG_DEBUG("trigger %d has unknown type %d", i, type);
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continue;
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}
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if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
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// Trigger is already in use, presumably by user code.
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if (result != ERROR_OK) {
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continue;
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}
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// address/data match trigger
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tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
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tdata1 = set_field(tdata1, MCONTROL_ACTION,
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MCONTROL_ACTION_DEBUG_MODE);
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tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
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tdata1 |= MCONTROL_M;
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if (info->misa & (1 << ('H' - 'A')))
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tdata1 |= MCONTROL_H;
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if (info->misa & (1 << ('S' - 'A')))
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tdata1 |= MCONTROL_S;
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if (info->misa & (1 << ('U' - 'A')))
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tdata1 |= MCONTROL_U;
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if (trigger->execute)
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tdata1 |= MCONTROL_EXECUTE;
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if (trigger->read)
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tdata1 |= MCONTROL_LOAD;
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if (trigger->write)
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tdata1 |= MCONTROL_STORE;
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write_csr(target, CSR_TDATA1, tdata1);
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uint64_t tdata1_rb;
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read_csr(target, &tdata1_rb, CSR_TDATA1);
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LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
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if (tdata1 != tdata1_rb) {
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LOG_DEBUG("Trigger %d doesn't support what we need; After writing 0x%"
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PRIx64 " to tdata1 it contains 0x%" PRIx64,
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i, tdata1, tdata1_rb);
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write_csr(target, CSR_TDATA1, 0);
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continue;
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}
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write_csr(target, CSR_TDATA2, trigger->address);
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LOG_DEBUG("Using resource %d for bp %d", i,
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trigger->unique_id);
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info->trigger_unique_id[i] = trigger->unique_id;
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@ -1898,8 +1976,13 @@ static int examine(struct target *target)
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update_reg_list(target);
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if (read_csr(target, &info->misa, CSR_MISA) != ERROR_OK) {
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LOG_ERROR("Failed to read misa.");
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return ERROR_FAIL;
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LOG_WARNING("Failed to read misa at 0x%x.", CSR_MISA);
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if (read_csr(target, &info->misa, 0xf10) != ERROR_OK) {
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// Maybe this is an old core that still has $misa at the old
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// address.
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LOG_ERROR("Failed to read misa at 0x%x.", 0xf10);
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return ERROR_FAIL;
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}
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}
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info->never_halted = true;
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@ -2129,6 +2212,9 @@ static int handle_halt(struct target *target, bool announce)
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write_csr(target, CSR_TSELECT, info->trigger_count);
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uint64_t tselect_rb;
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read_csr(target, &tselect_rb, CSR_TSELECT);
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// Mask off the top bit, which is used as tdrmode in old
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// implementations.
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tselect_rb &= ~(1ULL << (riscv_xlen(target)-1));
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if (info->trigger_count != tselect_rb)
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break;
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uint64_t tdata1;
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@ -707,7 +707,7 @@ static int init_target(struct command_context *cmd_ctx,
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LOG_DEBUG("init");
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riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
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riscv_info_init(generic_info);
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riscv_info_init(target, generic_info);
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generic_info->get_register = &riscv013_get_register;
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generic_info->set_register = &riscv013_set_register;
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generic_info->select_current_hart = &riscv013_select_current_hart;
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@ -834,6 +834,9 @@ static int add_trigger(struct target *target, struct trigger *trigger)
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uint64_t tdata1_rb;
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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riscv_set_current_hartid(target, hartid);
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if (hartid > 0) {
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@ -920,6 +923,9 @@ static int remove_trigger(struct target *target, struct trigger *trigger)
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}
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LOG_DEBUG("Stop using resource %d for bp %d", i, trigger->unique_id);
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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riscv_set_current_hartid(target, hartid);
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register_write_direct(target, GDB_REGNO_TSELECT, i);
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register_write_direct(target, GDB_REGNO_TDATA1, 0);
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@ -1125,17 +1131,23 @@ static int examine(struct target *target)
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/* Before doing anything else we must first enumerate the harts. */
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RISCV_INFO(r);
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if (riscv_rtos_enabled(target)) {
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for (int i = 0; i < RISCV_MAX_HARTS; ++i) {
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riscv_set_current_hartid(target, i);
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uint32_t s = dmi_read(target, DMI_DMSTATUS);
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if (get_field(s, DMI_DMSTATUS_ANYNONEXISTENT))
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break;
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r->hart_count = i + 1;
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int original_coreid = target->coreid;
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for (int i = 0; i < RISCV_MAX_HARTS; ++i) {
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/* Fake being a non-RTOS targeted to this core so we can see if
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* it exists. This avoids the assertion in
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* riscv_set_current_hartid() that ensures non-RTOS targets
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* don't touch the harts they're not assigned to. */
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target->coreid = i;
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r->hart_count = i + 1;
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riscv_set_current_hartid(target, i);
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uint32_t s = dmi_read(target, DMI_DMSTATUS);
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if (get_field(s, DMI_DMSTATUS_ANYNONEXISTENT)) {
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r->hart_count--;
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break;
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}
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} else {
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r->hart_count = 1;
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}
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target->coreid = original_coreid;
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LOG_DEBUG("Enumerated %d harts", r->hart_count);
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@ -1145,6 +1157,9 @@ static int examine(struct target *target)
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/* Find the address of the program buffer, which must be done without
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* knowing anything about the target. */
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for (int i = 0; i < riscv_count_harts(target); ++i) {
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if (!riscv_hart_enabled(target, i))
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continue;
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riscv_set_current_hartid(target, i);
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/* Without knowing anything else we can at least mess with the
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@ -1177,6 +1192,16 @@ static int examine(struct target *target)
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* In order to make this work we first need to */
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int offset = (progbuf_addr % 8 == 0) ? -4 : 0;
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/* This program uses a temporary register. If the core can not
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* execute 64 bit instruction, the original value of temporary
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* register (s0) will not be restored due to an exception.
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* So we have to save it and restore manually in that case.
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* If the core can execute 64 bit instruction, the saved value
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* is wrong, because it was read with 32 bit lw instruction,
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* but the value of s0 will be restored by the reverse swap
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* of s0 and dscratch registers. */
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uint64_t s0 = riscv_get_register(target, GDB_REGNO_S0);
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struct riscv_program program64;
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riscv_program_init(&program64, target);
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riscv_program_csrrw(&program64, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH);
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@ -1192,6 +1217,8 @@ static int examine(struct target *target)
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+ dmi_read(target, DMI_PROGBUF0 + (4 + offset) / 4)
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- 4;
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r->xlen[i] = 64;
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} else {
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riscv_set_register(target, GDB_REGNO_S0, s0);
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}
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/* Display this as early as possible to help people who are using
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@ -1215,6 +1242,9 @@ static int examine(struct target *target)
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/* Then we check the number of triggers availiable to each hart. */
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for (int i = 0; i < riscv_count_harts(target); ++i) {
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if (!riscv_hart_enabled(target, i))
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continue;
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for (uint32_t t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
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riscv_set_current_hartid(target, i);
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@ -1229,6 +1259,7 @@ static int examine(struct target *target)
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/* Resumes all the harts, so the debugger can later pause them. */
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riscv_resume_all_harts(target);
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target->state = TARGET_RUNNING;
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target_set_examined(target);
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if (target->rtos) {
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@ -1323,9 +1354,6 @@ static int read_memory(struct target *target, target_addr_t address,
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size, address);
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select_dmi(target);
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/* There was a bug in the memory system and only accesses from hart 0 actually
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* worked correctly. This should be obselete now. -palmer */
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riscv_set_current_hartid(target, 0);
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/* This program uses two temporary registers. A word of data and the
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* associated address are stored at some location in memory. The
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@ -1521,9 +1549,6 @@ static int write_memory(struct target *target, target_addr_t address,
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LOG_DEBUG("writing %d words of %d bytes to 0x%08lx", count, size, (long)address);
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select_dmi(target);
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/* There was a bug in the memory system and only accesses from hart 0 actually
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* worked correctly. This should be obselete now. -palmer */
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riscv_set_current_hartid(target, 0);
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/* This program uses two temporary registers. A word of data and the
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* associated address are stored at some location in memory. The
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|
|
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@ -448,11 +448,12 @@ static int riscv_get_gdb_reg_list(struct target *target,
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{
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RISCV_INFO(r);
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LOG_DEBUG("reg_class=%d", reg_class);
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LOG_DEBUG("riscv_get_gdb_reg_list: rtos_hartid=%d current_hartid=%d", r->rtos_hartid, r->current_hartid);
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if (r->rtos_hartid != -1)
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LOG_DEBUG("rtos_hartid=%d current_hartid=%d", r->rtos_hartid, r->current_hartid);
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if (r->rtos_hartid != -1 && riscv_rtos_enabled(target))
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riscv_set_current_hartid(target, r->rtos_hartid);
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else
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riscv_set_current_hartid(target, 0);
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riscv_set_current_hartid(target, target->coreid);
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|
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switch (reg_class) {
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case REG_CLASS_GENERAL:
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||||
|
|
@ -877,11 +878,12 @@ struct target_type riscv_target =
|
|||
|
||||
/*** RISC-V Interface ***/
|
||||
|
||||
void riscv_info_init(riscv_info_t *r)
|
||||
void riscv_info_init(struct target *target, riscv_info_t *r)
|
||||
{
|
||||
memset(r, 0, sizeof(*r));
|
||||
r->dtm_version = 1;
|
||||
r->registers_initialized = false;
|
||||
r->current_hartid = target->coreid;
|
||||
|
||||
for (size_t h = 0; h < RISCV_MAX_HARTS; ++h) {
|
||||
r->xlen[h] = -1;
|
||||
|
|
@ -894,11 +896,11 @@ void riscv_info_init(riscv_info_t *r)
|
|||
|
||||
int riscv_halt_all_harts(struct target *target)
|
||||
{
|
||||
if (riscv_rtos_enabled(target)) {
|
||||
for (int i = 0; i < riscv_count_harts(target); ++i)
|
||||
riscv_halt_one_hart(target, i);
|
||||
} else {
|
||||
riscv_halt_one_hart(target, riscv_current_hartid(target));
|
||||
for (int i = 0; i < riscv_count_harts(target); ++i) {
|
||||
if (!riscv_hart_enabled(target, i))
|
||||
continue;
|
||||
|
||||
riscv_halt_one_hart(target, i);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
|
|
@ -920,11 +922,11 @@ int riscv_halt_one_hart(struct target *target, int hartid)
|
|||
|
||||
int riscv_resume_all_harts(struct target *target)
|
||||
{
|
||||
if (riscv_rtos_enabled(target)) {
|
||||
for (int i = 0; i < riscv_count_harts(target); ++i)
|
||||
riscv_resume_one_hart(target, i);
|
||||
} else {
|
||||
riscv_resume_one_hart(target, riscv_current_hartid(target));
|
||||
for (int i = 0; i < riscv_count_harts(target); ++i) {
|
||||
if (!riscv_hart_enabled(target, i))
|
||||
continue;
|
||||
|
||||
riscv_resume_one_hart(target, i);
|
||||
}
|
||||
|
||||
riscv_invalidate_register_cache(target);
|
||||
|
|
@ -948,11 +950,11 @@ int riscv_resume_one_hart(struct target *target, int hartid)
|
|||
|
||||
int riscv_reset_all_harts(struct target *target)
|
||||
{
|
||||
if (riscv_rtos_enabled(target)) {
|
||||
for (int i = 0; i < riscv_count_harts(target); ++i)
|
||||
riscv_reset_one_hart(target, i);
|
||||
} else {
|
||||
riscv_reset_one_hart(target, riscv_current_hartid(target));
|
||||
for (int i = 0; i < riscv_count_harts(target); ++i) {
|
||||
if (!riscv_hart_enabled(target, i))
|
||||
continue;
|
||||
|
||||
riscv_reset_one_hart(target, i);
|
||||
}
|
||||
|
||||
riscv_invalidate_register_cache(target);
|
||||
|
|
@ -1022,10 +1024,9 @@ void riscv_set_current_hartid(struct target *target, int hartid)
|
|||
|
||||
int previous_hartid = riscv_current_hartid(target);
|
||||
r->current_hartid = hartid;
|
||||
assert(riscv_rtos_enabled(target) || target->coreid == hartid);
|
||||
assert(riscv_hart_enabled(target, hartid));
|
||||
LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
|
||||
if (riscv_rtos_enabled(target))
|
||||
r->select_current_hart(target);
|
||||
r->select_current_hart(target);
|
||||
|
||||
/* This might get called during init, in which case we shouldn't be
|
||||
* setting up the register cache. */
|
||||
|
|
@ -1073,10 +1074,7 @@ void riscv_invalidate_register_cache(struct target *target)
|
|||
int riscv_current_hartid(const struct target *target)
|
||||
{
|
||||
RISCV_INFO(r);
|
||||
if (riscv_rtos_enabled(target))
|
||||
return r->current_hartid;
|
||||
else
|
||||
return target->coreid;
|
||||
return r->current_hartid;
|
||||
}
|
||||
|
||||
void riscv_set_all_rtos_harts(struct target *target)
|
||||
|
|
@ -1242,6 +1240,15 @@ int riscv_dmi_write_u64_bits(struct target *target)
|
|||
return r->dmi_write_u64_bits(target);
|
||||
}
|
||||
|
||||
bool riscv_hart_enabled(struct target *target, int hartid)
|
||||
{
|
||||
/* FIXME: Add a hart mask to the RTOS. */
|
||||
if (riscv_rtos_enabled(target))
|
||||
return hartid < riscv_count_harts(target);
|
||||
|
||||
return hartid == target->coreid;
|
||||
}
|
||||
|
||||
/* Command Handlers */
|
||||
|
||||
COMMAND_HANDLER(riscv_test_compliance) {
|
||||
|
|
|
|||
|
|
@ -135,7 +135,7 @@ int riscv_openocd_deassert_reset(struct target *target);
|
|||
/*** RISC-V Interface ***/
|
||||
|
||||
/* Initializes the shared RISC-V structure. */
|
||||
void riscv_info_init(riscv_info_t *r);
|
||||
void riscv_info_init(struct target *target, riscv_info_t *r);
|
||||
|
||||
/* Run control, possibly for multiple harts. The _all_harts versions resume
|
||||
* all the enabled harts, which when running in RTOS mode is all the harts on
|
||||
|
|
@ -216,4 +216,7 @@ int riscv_dmi_write_u64_bits(struct target *target);
|
|||
/* Invalidates the register cache. */
|
||||
void riscv_invalidate_register_cache(struct target *target);
|
||||
|
||||
/* Returns TRUE when a hart is enabled in this target. */
|
||||
bool riscv_hart_enabled(struct target *target, int hartid);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue