armv7a: fix handling of inner caches
ARMv7 architecture allows up to 7 cache levels that are architecturally visible, as opposed to "system caches", which are outside of the domain defined by ARMv7 and require separate management. This patch enables detection and identification of caches at all levels. It also implements a new "flush-all" function that cleans & invalidates all cache levels to the "Point of Coherence". Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3024 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins__archive__
Matthias Welwarsky
Paul Fertser
parent
3a292a1f34
commit
8704e53665
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@ -379,24 +379,42 @@ done:
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static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ctx,
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struct armv7a_cache_common *armv7a_cache)
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{
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if (armv7a_cache->ctype == -1) {
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int cl;
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if (armv7a_cache->info == -1) {
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command_print(cmd_ctx, "cache not yet identified");
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return ERROR_OK;
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}
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command_print(cmd_ctx,
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"D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
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armv7a_cache->d_u_size.linelen,
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armv7a_cache->d_u_size.associativity,
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armv7a_cache->d_u_size.nsets,
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armv7a_cache->d_u_size.cachesize);
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for (cl = 0; cl < armv7a_cache->loc; cl++) {
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struct armv7a_arch_cache *arch = &(armv7a_cache->arch[cl]);
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command_print(cmd_ctx,
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"I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
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armv7a_cache->i_size.linelen,
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armv7a_cache->i_size.associativity,
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armv7a_cache->i_size.nsets,
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armv7a_cache->i_size.cachesize);
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if (arch->ctype & 1) {
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command_print(cmd_ctx,
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"L%d I-Cache: linelen %" PRIi32
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", associativity %" PRIi32
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", nsets %" PRIi32
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", cachesize %" PRId32 " KBytes",
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cl+1,
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arch->i_size.linelen,
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arch->i_size.associativity,
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arch->i_size.nsets,
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arch->i_size.cachesize);
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}
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if (arch->ctype >= 2) {
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command_print(cmd_ctx,
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"L%d D-Cache: linelen %" PRIi32
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", associativity %" PRIi32
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", nsets %" PRIi32
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", cachesize %" PRId32 " KBytes",
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cl+1,
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arch->d_u_size.linelen,
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arch->d_u_size.associativity,
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arch->d_u_size.nsets,
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arch->d_u_size.cachesize);
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}
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}
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return ERROR_OK;
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}
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@ -457,7 +475,7 @@ int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
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struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
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(armv7a_cache->outer_cache);
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if (armv7a_cache->ctype == -1) {
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if (armv7a_cache->info == -1) {
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command_print(cmd_ctx, "cache not yet identified");
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return ERROR_OK;
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}
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@ -517,17 +535,61 @@ done:
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}
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static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
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{
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int retval = ERROR_OK;
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/* select cache level */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
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(cl << 1) | (ct == 1 ? 1 : 0));
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if (retval != ERROR_OK)
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goto done;
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
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cache_reg);
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done:
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return retval;
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}
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static struct armv7a_cachesize decode_cache_reg(uint32_t cache_reg)
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{
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struct armv7a_cachesize size;
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int i = 0;
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size.linelen = 16 << (cache_reg & 0x7);
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size.associativity = ((cache_reg >> 3) & 0x3ff) + 1;
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size.nsets = ((cache_reg >> 13) & 0x7fff) + 1;
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size.cachesize = size.linelen * size.associativity * size.nsets / 1024;
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/* compute info for set way operation on cache */
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size.index_shift = (cache_reg & 0x7) + 4;
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size.index = (cache_reg >> 13) & 0x7fff;
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size.way = ((cache_reg >> 3) & 0x3ff);
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while (((size.way << i) & 0x80000000) == 0)
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i++;
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size.way_shift = i;
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return size;
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}
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int armv7a_identify_cache(struct target *target)
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{
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/* read cache descriptor */
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int retval = ERROR_FAIL;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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uint32_t cache_selected, clidr, ctr;
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uint32_t cache_i_reg, cache_d_reg;
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struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
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uint32_t csselr, clidr, ctr;
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uint32_t cache_reg;
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int cl, ctype;
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struct armv7a_cache_common *cache =
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&(armv7a->armv7a_mmu.armv7a_cache);
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if (!armv7a->is_armv7r)
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armv7a_read_ttbcr(target);
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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@ -552,120 +614,79 @@ int armv7a_identify_cache(struct target *target)
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&clidr);
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if (retval != ERROR_OK)
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goto done;
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clidr = (clidr & 0x7000000) >> 23;
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LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
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if ((clidr / 2) > 1) {
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/* FIXME not supported present in cortex A8 and later */
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/* in cortex A7, A15 */
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LOG_ERROR("cache l2 present :not supported");
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}
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/* retrieve selected cache
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cache->loc = (clidr & 0x7000000) >> 24;
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LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
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/* retrieve selected cache for later restore
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* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
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&cache_selected);
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&csselr);
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if (retval != ERROR_OK)
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goto done;
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retval = armv7a->arm.mrc(target, 15,
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2, 0, /* op1, op2 */
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0, 0, /* CRn, CRm */
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&cache_selected);
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if (retval != ERROR_OK)
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goto done;
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/* select instruction cache
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* MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
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* [0] : 1 instruction cache selection , 0 data cache selection */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
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1);
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if (retval != ERROR_OK)
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goto done;
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/* retrieve all available inner caches */
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for (cl = 0; cl < cache->loc; clidr >>= 3, cl++) {
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/* read CCSIDR
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* MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
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* [2:0] line size 001 eight word per line
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* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
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&cache_i_reg);
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if (retval != ERROR_OK)
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goto done;
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/* isolate cache type at current level */
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ctype = clidr & 7;
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/* select data cache*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
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0);
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if (retval != ERROR_OK)
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goto done;
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/* skip reserved values */
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if (ctype > CACHE_LEVEL_HAS_UNIFIED_CACHE)
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continue;
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
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&cache_d_reg);
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if (retval != ERROR_OK)
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goto done;
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/* separate d or unified d/i cache at this level ? */
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if (ctype & (CACHE_LEVEL_HAS_UNIFIED_CACHE | CACHE_LEVEL_HAS_D_CACHE)) {
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/* retrieve d-cache info */
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retval = get_cache_info(dpm, cl, 0, &cache_reg);
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if (retval != ERROR_OK)
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goto done;
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cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
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LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
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cache->arch[cl].d_u_size.index,
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cache->arch[cl].d_u_size.index_shift,
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cache->arch[cl].d_u_size.way,
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cache->arch[cl].d_u_size.way_shift);
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LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
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cache->arch[cl].d_u_size.linelen,
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cache->arch[cl].d_u_size.cachesize,
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cache->arch[cl].d_u_size.associativity);
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}
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/* separate i-cache at this level ? */
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if (ctype & CACHE_LEVEL_HAS_I_CACHE) {
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/* retrieve i-cache info */
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retval = get_cache_info(dpm, cl, 1, &cache_reg);
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if (retval != ERROR_OK)
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goto done;
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cache->arch[cl].i_size = decode_cache_reg(cache_reg);
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LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
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cache->arch[cl].i_size.index,
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cache->arch[cl].i_size.index_shift,
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cache->arch[cl].i_size.way,
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cache->arch[cl].i_size.way_shift);
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LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
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cache->arch[cl].i_size.linelen,
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cache->arch[cl].i_size.cachesize,
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cache->arch[cl].i_size.associativity);
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}
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cache->arch[cl].ctype = ctype;
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}
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/* restore selected cache */
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dpm->instr_write_data_r0(dpm,
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ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
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cache_selected);
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csselr);
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if (retval != ERROR_OK)
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goto done;
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dpm->finish(dpm);
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/* put fake type */
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cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
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cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
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cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
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cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) + 1;
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/* compute info for set way operation on cache */
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cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
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cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
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cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
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cache->d_u_size.way_shift = cache->d_u_size.way + 1;
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{
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int i = 0;
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while (((cache->d_u_size.way_shift >> i) & 1) != 1)
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i++;
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cache->d_u_size.way_shift = 32-i;
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}
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#if 0
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LOG_INFO("data cache index %d << %d, way %d << %d",
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cache->d_u_size.index, cache->d_u_size.index_shift,
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cache->d_u_size.way,
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cache->d_u_size.way_shift);
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LOG_INFO("data cache %d bytes %d KBytes asso %d ways",
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cache->d_u_size.linelen,
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cache->d_u_size.cachesize,
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cache->d_u_size.associativity);
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#endif
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cache->i_size.linelen = 16 << (cache_i_reg & 0x7);
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cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) + 1;
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cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff;
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cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8;
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/* compute info for set way operation on cache */
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cache->i_size.index_shift = (cache_i_reg & 0x7) + 4;
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cache->i_size.index = (cache_i_reg >> 13) & 0x7fff;
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cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff);
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cache->i_size.way_shift = cache->i_size.way + 1;
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{
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int i = 0;
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while (((cache->i_size.way_shift >> i) & 1) != 1)
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i++;
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cache->i_size.way_shift = 32-i;
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}
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#if 0
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LOG_INFO("instruction cache index %d << %d, way %d << %d",
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cache->i_size.index, cache->i_size.index_shift,
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cache->i_size.way, cache->i_size.way_shift);
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LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways",
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cache->i_size.linelen,
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cache->i_size.cachesize,
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cache->i_size.associativity);
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#endif
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/* if no l2 cache initialize l1 data cache flush function function */
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if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache == NULL) {
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armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
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@ -673,8 +694,8 @@ int armv7a_identify_cache(struct target *target)
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armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
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armv7a_cache_auto_flush_all_data;
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}
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armv7a->armv7a_mmu.armv7a_cache.ctype = 0;
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armv7a->armv7a_mmu.armv7a_cache.info = 1;
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done:
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dpm->finish(dpm);
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armv7a_read_mpidr(target);
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@ -691,7 +712,7 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
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armv7a->arm.target = target;
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armv7a->arm.common_magic = ARM_COMMON_MAGIC;
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armv7a->common_magic = ARMV7_COMMON_MAGIC;
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armv7a->armv7a_mmu.armv7a_cache.ctype = -1;
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armv7a->armv7a_mmu.armv7a_cache.info = -1;
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armv7a->armv7a_mmu.armv7a_cache.outer_cache = NULL;
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armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
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armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL;
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@ -63,12 +63,20 @@ struct armv7a_cachesize {
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uint32_t way_shift;
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};
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struct armv7a_cache_common {
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int ctype;
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/* information about one architecture cache at any level */
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struct armv7a_arch_cache {
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int ctype; /* cache type, CLIDR encoding */
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struct armv7a_cachesize d_u_size; /* data cache */
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struct armv7a_cachesize i_size; /* instruction cache */
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};
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/* common cache information */
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struct armv7a_cache_common {
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int info; /* -1 invalid, else valid */
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int loc; /* level of coherency */
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uint32_t dminline; /* minimum d-cache linelen */
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uint32_t iminline; /* minimum i-cache linelen */
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struct armv7a_arch_cache arch[6]; /* cache info, L1 - L7 */
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int i_cache_enabled;
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int d_u_cache_enabled;
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int auto_cache_enabled; /* openocd automatic
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@ -60,28 +60,17 @@ static int armv7a_l1_i_cache_sanity_check(struct target *target)
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return ERROR_OK;
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}
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static int armv7a_l1_d_cache_clean_inval_all(struct target *target)
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static int armv7a_l1_d_cache_flush_level(struct arm_dpm *dpm, struct armv7a_cachesize *size, int cl)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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struct armv7a_cachesize *d_u_size =
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&(armv7a->armv7a_mmu.armv7a_cache.d_u_size);
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int32_t c_way, c_index = d_u_size->index;
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int retval;
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retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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int retval = ERROR_OK;
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int32_t c_way, c_index = size->index;
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LOG_DEBUG("cl %" PRId32, cl);
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do {
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c_way = d_u_size->way;
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c_way = size->way;
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do {
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uint32_t value = (c_index << d_u_size->index_shift)
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| (c_way << d_u_size->way_shift);
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uint32_t value = (c_index << size->index_shift)
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| (c_way << size->way_shift) | (cl << 1);
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/*
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* DCCISW - Clean and invalidate data cache
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* line by Set/Way.
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|
|
@ -96,6 +85,35 @@ static int armv7a_l1_d_cache_clean_inval_all(struct target *target)
|
|||
c_index -= 1;
|
||||
} while (c_index >= 0);
|
||||
|
||||
done:
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int armv7a_l1_d_cache_clean_inval_all(struct target *target)
|
||||
{
|
||||
struct armv7a_common *armv7a = target_to_armv7a(target);
|
||||
struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
|
||||
struct arm_dpm *dpm = armv7a->arm.dpm;
|
||||
int cl;
|
||||
int retval;
|
||||
|
||||
retval = armv7a_l1_d_cache_sanity_check(target);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = dpm->prepare(dpm);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
for (cl = 0; cl < cache->loc; cl++) {
|
||||
/* skip i-only caches */
|
||||
if (cache->arch[cl].ctype < CACHE_LEVEL_HAS_D_CACHE)
|
||||
continue;
|
||||
|
||||
armv7a_l1_d_cache_flush_level(dpm, &cache->arch[cl].d_u_size, cl);
|
||||
}
|
||||
|
||||
retval = dpm->finish(dpm);
|
||||
return retval;
|
||||
|
||||
done:
|
||||
|
|
|
|||
|
|
@ -30,4 +30,9 @@ int armv7a_cache_auto_flush_all_data(struct target *target);
|
|||
|
||||
extern const struct command_registration arm7a_cache_command_handlers[];
|
||||
|
||||
/* CLIDR cache types */
|
||||
#define CACHE_LEVEL_HAS_UNIFIED_CACHE 0x4
|
||||
#define CACHE_LEVEL_HAS_D_CACHE 0x2
|
||||
#define CACHE_LEVEL_HAS_I_CACHE 0x1
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -179,7 +179,7 @@ static int arm7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
|
|||
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
|
||||
(armv7a_cache->outer_cache);
|
||||
|
||||
if (armv7a_cache->ctype == -1) {
|
||||
if (armv7a_cache->info == -1) {
|
||||
command_print(cmd_ctx, "cache not yet identified");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1305,7 +1305,7 @@ static int cortex_a_post_debug_entry(struct target *target)
|
|||
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg);
|
||||
cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
|
||||
|
||||
if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1)
|
||||
if (armv7a->armv7a_mmu.armv7a_cache.info == -1)
|
||||
armv7a_identify_cache(target);
|
||||
|
||||
if (armv7a->is_armv7r) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue