riscv-013: Correct sign extension of address on read_memory

race
Megan Wachs 2017-05-01 09:37:48 -07:00
parent ad1cf13ef4
commit 8462750357
1 changed files with 2 additions and 2 deletions

View File

@ -1265,7 +1265,7 @@ static int read_memory(struct target *target, uint32_t address,
* program execution mechanism. */ * program execution mechanism. */
switch (riscv_xlen(target)) { switch (riscv_xlen(target)) {
case 64: case 64:
riscv_program_write_ram(&program, r_addr + 4, ((riscv_addr_t)(address - size)) >> 32); riscv_program_write_ram(&program, r_addr + 4, (((riscv_addr_t)(address)) - size) >> 32);
case 32: case 32:
riscv_program_write_ram(&program, r_addr, (riscv_addr_t)(address - size)); riscv_program_write_ram(&program, r_addr, (riscv_addr_t)(address - size));
break; break;
@ -1318,7 +1318,7 @@ static int read_memory(struct target *target, uint32_t address,
* the data was all copied. */ * the data was all copied. */
riscv_addr_t cur_addr = 0xbadbeef; riscv_addr_t cur_addr = 0xbadbeef;
riscv_addr_t fin_addr = address + (count * size); riscv_addr_t fin_addr = address + (count * size);
riscv_addr_t prev_addr = address - size; riscv_addr_t prev_addr = ((riscv_addr_t) address) - size;
LOG_DEBUG("writing until final address 0x%016lx", fin_addr); LOG_DEBUG("writing until final address 0x%016lx", fin_addr);
while (count > 1 && (cur_addr = riscv_read_debug_buffer_x(target, d_addr)) < fin_addr) { while (count > 1 && (cur_addr = riscv_read_debug_buffer_x(target, d_addr)) < fin_addr) {
LOG_DEBUG("transferring burst starting at address 0x%016lx (previous burst was 0x%016lx)", cur_addr, prev_addr); LOG_DEBUG("transferring burst starting at address 0x%016lx (previous burst was 0x%016lx)", cur_addr, prev_addr);