riscv-013: Correct sign extension of address on read_memory
parent
ad1cf13ef4
commit
8462750357
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@ -1265,7 +1265,7 @@ static int read_memory(struct target *target, uint32_t address,
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* program execution mechanism. */
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* program execution mechanism. */
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switch (riscv_xlen(target)) {
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switch (riscv_xlen(target)) {
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case 64:
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case 64:
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riscv_program_write_ram(&program, r_addr + 4, ((riscv_addr_t)(address - size)) >> 32);
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riscv_program_write_ram(&program, r_addr + 4, (((riscv_addr_t)(address)) - size) >> 32);
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case 32:
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case 32:
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riscv_program_write_ram(&program, r_addr, (riscv_addr_t)(address - size));
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riscv_program_write_ram(&program, r_addr, (riscv_addr_t)(address - size));
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break;
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break;
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@ -1318,7 +1318,7 @@ static int read_memory(struct target *target, uint32_t address,
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* the data was all copied. */
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* the data was all copied. */
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riscv_addr_t cur_addr = 0xbadbeef;
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riscv_addr_t cur_addr = 0xbadbeef;
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riscv_addr_t fin_addr = address + (count * size);
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riscv_addr_t fin_addr = address + (count * size);
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riscv_addr_t prev_addr = address - size;
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riscv_addr_t prev_addr = ((riscv_addr_t) address) - size;
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LOG_DEBUG("writing until final address 0x%016lx", fin_addr);
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LOG_DEBUG("writing until final address 0x%016lx", fin_addr);
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while (count > 1 && (cur_addr = riscv_read_debug_buffer_x(target, d_addr)) < fin_addr) {
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while (count > 1 && (cur_addr = riscv_read_debug_buffer_x(target, d_addr)) < fin_addr) {
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LOG_DEBUG("transferring burst starting at address 0x%016lx (previous burst was 0x%016lx)", cur_addr, prev_addr);
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LOG_DEBUG("transferring burst starting at address 0x%016lx (previous burst was 0x%016lx)", cur_addr, prev_addr);
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