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armv7m: use consistent arm.cpsr member 

We already set cpsr in armv7m_build_reg_cache, so lets use it for all other
accesses to this field.

Change-Id: I19b3b21ecf1571bbea12e1be664845e6544f6fa1
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1539
Tested-by: jenkins
__archive__
Spencer Oliver 2013-08-05 17:46:09 +01:00
parent 32ac9c0144
commit 83f1c6f916
3 changed files with 4 additions and 4 deletions
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2
src/target/arm.h
View File

@ -97,7 +97,7 @@ struct arm {
/** Handle to the PC; valid in all core modes. */
struct reg *pc;
/** Handle to the CPSR; valid in all core modes. */
/** Handle to the CPSR/xPSR; valid in all core modes. */
struct reg *cpsr;
/** Handle to the SPSR; valid only in core modes with an SPSR. */

4
src/target/cortex_m.c
View File

@ -430,7 +430,7 @@ static int cortex_m3_debug_entry(struct target *target)
arm->read_core_reg(target, r, i, ARM_MODE_ANY);
}
r = arm->core_cache->reg_list + ARMV7M_xPSR;
r = arm->cpsr;
xPSR = buf_get_u32(r->value, 0, 32);
#ifdef ARMV7_GDB_HACKS
@ -732,7 +732,7 @@ static int cortex_m3_resume(struct target *target, int current,
r->valid = true;
/* Make sure we are in Thumb mode */
r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR;
r = armv7m->arm.cpsr;
buf_set_u32(r->value, 24, 1, 1);
r->dirty = true;
r->valid = true;

2
src/target/hla_target.c
View File

@ -427,7 +427,7 @@ static int adapter_debug_entry(struct target *target)
/* make sure we clear the vector catch bit */
adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
r = arm->core_cache->reg_list + ARMV7M_xPSR;
r = arm->cpsr;
xPSR = buf_get_u32(r->value, 0, 32);
/* Are we in an exception handler */