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armv7a: Improve parsing of MPIDR register to avoid error message for Cortex R5 

References:
- ARM DDI0406C ARMv7 Architecture Reference Manual, section B4.1.106
- ARM DDI0460D Cortex-R5 Technical Reference Manual section 4.3.6
- ARM 100048_0002_0 Cortex-A73 Technical Reference Manual section 4.5.2

Tested on: TMS570LC4357

Change-Id: Ie0d45fb697697f78cc4ad4e7a0116be9772590ba
Signed-off-by: Tommy Vestermark <tov@vestermark.dk>
Reviewed-on: http://openocd.zylin.com/5108
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
bscan_optimization
Tommy Vestermark 2019-04-11 20:40:36 +10:00 committed by Matthias Welwarsky
parent 33281a87b6
commit 83515b60c9
2 changed files with 16 additions and 13 deletions
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24
src/target/armv7a.c
View File

@ -307,23 +307,21 @@ static int armv7a_read_mpidr(struct target *target)
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto done; goto done;
/* ARMv7R uses a different format for MPIDR. /* Is register in Multiprocessing Extensions register format? */
* When configured uniprocessor (most R cores) it reads as 0. if (mpidr & MPIDR_MP_EXT) {
* This will need to be implemented for multiprocessor ARMv7R cores. */ LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
if (armv7a->is_armv7r) {
if (mpidr)
LOG_ERROR("MPIDR nonzero in ARMv7-R target");
goto done;
}
if (mpidr & 1<<31) {
armv7a->multi_processor_system = (mpidr >> 30) & 1; armv7a->multi_processor_system = (mpidr >> 30) & 1;
armv7a->multi_threading_processor = (mpidr >> 24) & 1;
armv7a->level2_id = (mpidr >> 16) & 0xf;
armv7a->cluster_id = (mpidr >> 8) & 0xf; armv7a->cluster_id = (mpidr >> 8) & 0xf;
armv7a->cpu_id = mpidr & 0x3; armv7a->cpu_id = mpidr & 0xf;
LOG_INFO("%s cluster %x core %x %s", target_name(target), LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
target_name(target),
armv7a->level2_id,
armv7a->cluster_id, armv7a->cluster_id,
armv7a->cpu_id, armv7a->cpu_id,
armv7a->multi_processor_system == 0 ? "multi core" : "mono core"); armv7a->multi_processor_system == 0 ? "multi core" : "mono core",
armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
} else } else
LOG_ERROR("MPIDR not in multiprocessor format"); LOG_ERROR("MPIDR not in multiprocessor format");

5
src/target/armv7a.h
View File

@ -108,6 +108,8 @@ struct armv7a_common {
struct adiv5_ap *debug_ap; struct adiv5_ap *debug_ap;
/* mdir */ /* mdir */
uint8_t multi_processor_system; uint8_t multi_processor_system;
uint8_t multi_threading_processor;
uint8_t level2_id;
uint8_t cluster_id; uint8_t cluster_id;
uint8_t cpu_id; uint8_t cpu_id;
bool is_armv7r; bool is_armv7r;
@ -183,6 +185,9 @@ static inline bool is_armv7a(struct armv7a_common *armv7a)
#define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3)) #define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
#define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2)) #define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
/* Masks for Multiprocessor Affinity Register */
#define MPIDR_MP_EXT (1UL << 31)
int armv7a_arch_state(struct target *target); int armv7a_arch_state(struct target *target);
int armv7a_identify_cache(struct target *target); int armv7a_identify_cache(struct target *target);
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a); int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);