pipistrello: ftdi-jtag/spartan6/jtagspi board

The Pipistrello is a low cost FPGA board with a Xilinx
Spartan6 LX45, a SPI flash and onboard FTDI JTAG.
This board is a good example use case for the jtagspi
flash driver talking through a proxy bitstream.

Change-Id: I04a80610ff825c36ebcb67b879507028eed141ad
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2846
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
__archive__
Robert Jordens 2015-07-01 23:29:34 -06:00 committed by Spencer Oliver
parent d25355473d
commit 804eefc259
3 changed files with 81 additions and 0 deletions

14
tcl/board/pipistrello.cfg Normal file
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# http://pipistrello.saanlima.com/
source [find interface/ftdi/pipistrello.cfg]
source [find cpld/xilinx-xc6s.cfg]
source [find cpld/jtagspi.cfg]
# example command to write bitstream, soft-cpu bios and runtime:
# openocd -f board/pipistrello.cfg -c "init;\
# jtagspi_init 0 bscan_spi_xc6slx45.bit;\
# jtagspi_program bitstream-pistrello.bin 0;\
# jtagspi_program bios.bin 0x170000;\
# jtagspi_program runtime.fbi 0x180000;\
# xc6s_program xc6s.tap;\
# exit"

54
tcl/cpld/xilinx-xc6s.cfg Normal file
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# xilinx spartan6
# http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME xc6s
}
# the 4 top bits (28:31) are the die stepping. ignore it.
jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
-expected-id 0x04000093 \
-expected-id 0x04001093 \
-expected-id 0x04002093 \
-expected-id 0x04004093 \
-expected-id 0x04024093 \
-expected-id 0x04008093 \
-expected-id 0x04028093 \
-expected-id 0x0400E093 \
-expected-id 0x0402E093 \
-expected-id 0x04011093 \
-expected-id 0x04031093 \
-expected-id 0x0401D093 \
-expected-id 0x0403D093
pld device virtex2 $_CHIPNAME.tap
set XC6S_CFG_IN 0x05
set XC6S_JSHUTDOWN 0x0d
set XC6S_JPROGRAM 0x0b
set XC6S_JSTART 0x0c
set XC6S_BYPASS 0x3f
proc xc6s_program {tap} {
global XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS
irscan $tap $XC6S_JSHUTDOWN
irscan $tap $XC6S_JPROGRAM
irscan $tap $XC6S_JSTART
irscan $tap $XC6S_BYPASS
}
#xtp038 and xc3sprog approach
proc xc6s_program_iprog {tap} {
global XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN
irscan $tap $XC6S_JSHUTDOWN
runtest 16
irscan $tap $XC6S_CFG_IN
# xtp038 IPROG 16bit flipped
drscan $tap 16 0xffff 16 0x9955 16 0x66aa 16 0x850c 16 0x7000 16 0x0004
irscan $tap $XC6S_JSTART
runtest 32
irscan $tap $XC6S_BYPASS
runtest 1
}

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# http://pipistrello.saanlima.com/
# http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdf
interface ftdi
ftdi_device_desc "Pipistrello LX45"
ftdi_vid_pid 0x0403 0x6010
# interface 1 is the uart
ftdi_channel 0
# just TCK TDI TDO TMS, no reset
ftdi_layout_init 0x0008 0x000b
reset_config none
# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
adapter_khz 30000