parent
a0623b2fa8
commit
7edd9b1786
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@ -767,9 +767,9 @@ static int register_write_direct(struct target *target, unsigned number,
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if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
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if (supports_extension(target, 'D') && riscv_xlen(target) >= 64) {
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riscv_program_insert(&program, fmv_x_d(S0, number - GDB_REGNO_FPR0));
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riscv_program_insert(&program, fmv_d_x(number - GDB_REGNO_FPR0, S0));
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} else {
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riscv_program_insert(&program, fmv_x_s(S0, number - GDB_REGNO_FPR0));
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riscv_program_insert(&program, fmv_s_x(number - GDB_REGNO_FPR0, S0));
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}
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} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
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riscv_program_csrw(&program, S0, number);
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@ -811,9 +811,9 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
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// TODO: Possibly set F in mstatus.
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// TODO: Fully support D extension on RV32.
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if (supports_extension(target, 'D') && riscv_xlen(target) >= 64) {
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riscv_program_insert(&program, fmv_d_x(number - GDB_REGNO_FPR0, S0));
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riscv_program_insert(&program, fmv_x_d(S0, number - GDB_REGNO_FPR0));
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} else {
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riscv_program_insert(&program, fmv_s_x(number - GDB_REGNO_FPR0, S0));
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riscv_program_insert(&program, fmv_x_s(S0, number - GDB_REGNO_FPR0));
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}
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} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
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riscv_program_csrr(&program, S0, number);
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@ -1086,9 +1086,12 @@ static int examine(struct target *target)
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r->xlen[i] = 32;
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}
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r->misa = riscv_get_register_on_hart(target, i, GDB_REGNO_MISA);
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/* Display this as early as possible to help people who are using
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* really slow simulators. */
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LOG_DEBUG(" hart %d: XLEN=%d", i, r->xlen[i]);
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LOG_DEBUG(" hart %d: XLEN=%d, misa=0x%" PRIx64, i, r->xlen[i],
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r->misa);
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}
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/* Then we check the number of triggers availiable to each hart. */
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