reset and post reset speed & jtag_khz command documented.
git-svn-id: svn://svn.berlios.de/openocd/trunk@515 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
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@ -273,12 +273,18 @@ Cirrus Logic EP93xx based single-board computer bit-banging (in development)
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@end itemize
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@itemize @bullet
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@item @b{jtag_speed} <@var{number}>
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@item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
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@cindex jtag_speed
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Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
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speed. The actual effect of this option depends on the JTAG interface used.
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speed. The actual effect of this option depends on the JTAG interface used. Reset
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speed is used during reset and post reset speed after reset. post reset speed
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is optional, in which case the reset speed is used.
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@itemize @minus
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@item wiggler: maximum speed / @var{number}
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@item ft2232: 6MHz / (@var{number}+1)
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@item amt jtagaccel: 8 / 2**@var{number}
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@ -287,6 +293,13 @@ speed. The actual effect of this option depends on the JTAG interface used.
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Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
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especially true for synthesized cores (-S).
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@item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
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@cindex jtag_khz
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Same as jtag_speed, except that the speed is specified in maximum kHz. If
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the device can not support the rate asked for, or can not translate from
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kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
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is not supported, then an error is reported.
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@item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
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@cindex reset_config
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The configuration of the reset signals available on the JTAG interface AND the target.
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