From 7dd48acdc012612f2d102c7f25ade6514beda3dd Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 25 Nov 2016 09:46:55 -0800 Subject: [PATCH] Cope better if the target unexpectedly resets. Change-Id: I713f7f8a3afbbb02be0e2f19f4d32778366d37f9 --- src/target/riscv/riscv.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 6d2bf5b67..d4af3deb9 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -722,22 +722,29 @@ static bits_t read_bits(struct target *target) uint64_t value; dbus_status_t status; uint16_t address_in; + riscv_info_t *info = (riscv_info_t *) target->arch_info; + + bits_t err_result = { + .haltnot = 0, + .interrupt = 0 + }; do { unsigned i = 0; do { status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0); if (status == DBUS_STATUS_BUSY) { + if (address_in == (1<addrbits) - 1 && + value == (1ULL<= 256) { LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status); - bits_t err_result = { - .haltnot = 0, - .interrupt = 0 - }; return err_result; } } while (address_in > 0x10 && address_in != DMCONTROL);