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arm_dpm: flush both scratch registers (R0 and R1) 

Neither the initial loop to clear dirty registers (which visits all
registers starting at R2 and counting upwards) nor the final explicit
flushes ensure a write-back in arm_dpm_write_dirty_registers.

This change makes sure that both our scratch registers (i.e. R0 and
R1) are written back to the target.

Change-Id: If65be4f371cd40af9a0cfa97f3730b070b92e981
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-on: http://openocd.zylin.com/4506
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
riscv-compliance
Philipp Tomsich 2018-04-27 19:59:56 +02:00 committed by Matthias Welwarsky
parent aba11ae6e2
commit 7b94ae9e52
1 changed files with 7 additions and 5 deletions
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12
src/target/arm_dpm.c
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@ -587,11 +587,13 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
goto done;
arm->pc->dirty = false;
/* flush R0 -- it's *very* dirty by now */
retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
if (retval != ERROR_OK)
goto done;
cache->reg_list[0].dirty = false;
/* flush R0 and R1 (our scratch registers) */
for (unsigned i = 0; i < 2; i++) {
retval = dpm_write_reg(dpm, &cache->reg_list[i], i);
if (retval != ERROR_OK)
goto done;
cache->reg_list[i].dirty = false;
}
/* (void) */ dpm->finish(dpm);
done: