diff --git a/src/flash/lpc2000.c b/src/flash/lpc2000.c
index f35c0ba0e..e3c7e742b 100644
--- a/src/flash/lpc2000.c
+++ b/src/flash/lpc2000.c
@@ -350,7 +350,7 @@ int lpc2000_iap_blank_check(struct flash_bank_s *bank, int first, int last)
 	return ERROR_OK;
 }
 
-/* flash_bank lpc2000 <base> <size> 0 0 <lpc_variant> <target#> <cclk> [calc_checksum]
+/* flash bank lpc2000 <base> <size> 0 0 <lpc_variant> <target#> <cclk> [calc_checksum]
  */
 int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 {
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 0472155bd..47996de4f 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -118,7 +118,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * S: in priviledged mode: store user-mode registers
  * W=1: update the base register. W=0: leave the base register untouched
  */
-#define ARMV4_5_STMIA(Rn, List, S, W)	(0xe8800000 | (S << 22) | (W << 21) | (Rn << 16) | (List))
+#define ARMV4_5_STMIA(Rn, List, S, W)	(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 
 /* Load multiple increment after
  * Rn: base register
@@ -126,7 +126,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * S: in priviledged mode: store user-mode registers
  * W=1: update the base register. W=0: leave the base register untouched
  */
-#define ARMV4_5_LDMIA(Rn, List, S, W)	(0xe8900000 | (S << 22) | (W << 21) | (Rn << 16) | (List))
+#define ARMV4_5_LDMIA(Rn, List, S, W)	(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 
 /* MOV r8, r8 */
 #define ARMV4_5_NOP					(0xe1a08008)
@@ -135,19 +135,19 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * R=1: SPSR R=0: CPSR
  * Rn: target register
  */
-#define ARMV4_5_MRS(Rn, R)			(0xe10f0000 | (R << 22) | (Rn << 12))
+#define ARMV4_5_MRS(Rn, R)			(0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 
 /* Store register
  * Rd: register to store
  * Rn: base register
  */
-#define ARMV4_5_STR(Rd, Rn)			(0xe5800000 | (Rd << 12) | (Rn << 16))
+#define ARMV4_5_STR(Rd, Rn)			(0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 
 /* Load register
  * Rd: register to load
  * Rn: base register
  */
-#define ARMV4_5_LDR(Rd, Rn)			(0xe5900000 | (Rd << 12) | (Rn << 16))
+#define ARMV4_5_LDR(Rd, Rn)			(0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 
 /* Move general purpose register to PSR
  * R=1: SPSR R=0: CPSR
@@ -155,43 +155,43 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * 1: control field 2: extension field 4: status field 8: flags field
  * Rm: source register
  */
-#define ARMV4_5_MSR_GP(Rm, Field, R)	(0xe120f000 | Rm | (Field << 16) | (R << 22))
-#define ARMV4_5_MSR_IM(Im, Rotate, Field, R)	(0xe320f000 | (Im)  | (Rotate << 8) | (Field << 16) | (R << 22))
+#define ARMV4_5_MSR_GP(Rm, Field, R)	(0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
+#define ARMV4_5_MSR_IM(Im, Rotate, Field, R)	(0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 
 /* Load Register Halfword Immediate Post-Index
  * Rd: register to load
  * Rn: base register
  */
-#define ARMV4_5_LDRH_IP(Rd, Rn)	(0xe0d000b2 | (Rd << 12) | (Rn << 16))
+#define ARMV4_5_LDRH_IP(Rd, Rn)	(0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 
 /* Load Register Byte Immediate Post-Index
  * Rd: register to load
  * Rn: base register
  */
-#define ARMV4_5_LDRB_IP(Rd, Rn)	(0xe4d00001 | (Rd << 12) | (Rn << 16))
+#define ARMV4_5_LDRB_IP(Rd, Rn)	(0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 
 /* Store register Halfword Immediate Post-Index
  * Rd: register to store
  * Rn: base register
  */
-#define ARMV4_5_STRH_IP(Rd, Rn)	(0xe0c000b2 | (Rd << 12) | (Rn << 16))
+#define ARMV4_5_STRH_IP(Rd, Rn)	(0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 
 /* Store register Byte Immediate Post-Index
  * Rd: register to store
  * Rn: base register
  */
-#define ARMV4_5_STRB_IP(Rd, Rn)	(0xe4c00001 | (Rd << 12) | (Rn << 16))
+#define ARMV4_5_STRB_IP(Rd, Rn)	(0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 
 /* Branch (and Link)
  * Im: Branch target (left-shifted by 2 bits, added to PC)
  * L: 1: branch and link 0: branch only
  */
-#define ARMV4_5_B(Im, L) (0xea000000 | Im | (L << 24))
+#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 
 /* Branch and exchange (ARM state)
  * Rm: register holding branch target address
  */
-#define ARMV4_5_BX(Rm) (0xe12fff10 | Rm)
+#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 
 /* Move to ARM register from coprocessor
  * CP: Coprocessor number
@@ -201,7 +201,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * CRm: second coprocessor operand
  * op2: Second coprocessor opcode
  */
-#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | CRm | (op2 << 5) | (CP << 8) | (Rd << 12) | (CRn << 16) | (op1 << 21)) 
+#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 
 
 /* Move to coprocessor from ARM register
  * CP: Coprocessor number
@@ -211,7 +211,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * CRm: second coprocessor operand
  * op2: Second coprocessor opcode
  */
-#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | CRm | (op2 << 5) | (CP << 8) | (Rd << 12) | (CRn << 16) | (op1 << 21)) 
+#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 
 
 
 /* Thumb mode instructions
@@ -221,30 +221,30 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * Rd: source register
  * Rn: base register
  */
-#define ARMV4_5_T_STR(Rd, Rn)	((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
+#define ARMV4_5_T_STR(Rd, Rn)	((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 
 /* Load register (Thumb state)
  * Rd: destination register
  * Rn: base register
  */
-#define ARMV4_5_T_LDR(Rd, Rn)	((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
+#define ARMV4_5_T_LDR(Rd, Rn)	((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 
 /* Load multiple (Thumb state)
  * Rn: base register
  * List: for each bit in list: store register
  */
-#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
+#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
  
 /* Load register with PC relative addressing
  * Rd: register to load
  */
-#define ARMV4_5_T_LDR_PCREL(Rd)	((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) 
+#define ARMV4_5_T_LDR_PCREL(Rd)	((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) 
  
 /* Move hi register (Thumb mode)
  * Rd: destination register
  * Rm: source register
  */
-#define ARMV4_5_T_MOV(Rd, Rm)	((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
+#define ARMV4_5_T_MOV(Rd, Rm)	((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 
 /* No operation (Thumb mode)
  */
@@ -254,16 +254,16 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * Rd: destination register
  * Im: 8-bit immediate value
  */
-#define ARMV4_5_T_MOV_IM(Rd, Im)	((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
+#define ARMV4_5_T_MOV_IM(Rd, Im)	((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 
 /* Branch and Exchange
  * Rm: register containing branch target
  */
-#define ARMV4_5_T_BX(Rm)		((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
+#define ARMV4_5_T_BX(Rm)		((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 
 /* Branch (Thumb state)
  * Imm: Branch target
  */
-#define ARMV4_5_T_B(Imm)	((0xe000 | Imm) | ((0xe000 | Imm) << 16))
+#define ARMV4_5_T_B(Imm)	((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 
 #endif /* ARMV4_5_H */