Avoid cache invalidation when writing to hardware debug registers
git-svn-id: svn://svn.berlios.de/openocd/trunk@2733 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
parent
01735c515f
commit
781997f556
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@ -332,6 +332,21 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
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return retval;
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}
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/* Write to memory mapped registers directly with no cache or mmu handling */
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int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value)
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{
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int retval;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv7a_common_t *armv7a = armv4_5->arch_info;
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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retval = mem_ap_write_atomic_u32(swjdp, address, value);
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return retval;
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}
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/*
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* Cortex-A8 Run control
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*/
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@ -1022,10 +1037,10 @@ int cortex_a8_set_breakpoint(struct target_s *target,
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brp_list[brp_i].used = 1;
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brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
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brp_list[brp_i].control = control;
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target_write_u32(target, armv7a->debug_base
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cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
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+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
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brp_list[brp_i].value);
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target_write_u32(target, armv7a->debug_base
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cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
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+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
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brp_list[brp_i].control);
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LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
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@ -1088,10 +1103,10 @@ int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
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brp_list[brp_i].used = 0;
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brp_list[brp_i].value = 0;
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brp_list[brp_i].control = 0;
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target_write_u32(target, armv7a->debug_base
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cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
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+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
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brp_list[brp_i].control);
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target_write_u32(target, armv7a->debug_base
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cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
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+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
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brp_list[brp_i].value);
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}
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