Support for STM32F722, F723, F413 and F423
IDs for STM32F722, F723, F413 and F423 added, handling of PCROP for F722/723 and additional nWPRT bits for F413/423 implemented. The additional protection bit positions for F413/423 conflict with other options bits for the F7xx variants, additionally the last two sectors share a common bit. Protection for F413 and F767/777 now use protection blocks rather sectors for dealing with protections bits. Checking for halted state in 'lock' and 'unlock' removed: When PCROP is activated in F723, halted state is not detected properly, but lock/unlock sequence is required to disable PCROP. Tested with STM32F723E-Disco, STM32F413ZH-Nucleo. Change-Id: Ie6ddab47a9ae8461087d369b4f289b7f9d1e031c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4045 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>macbuild
Andreas Bolsch
Spencer Oliver
parent
3ee81fd787
commit
7719e9618e
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@ -5989,16 +5989,21 @@ The @var{num} parameter is a value shown by @command{flash banks}.
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@end deffn
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@deffn Command {stm32f2x options_read} num
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Reads and displays user options and (where implemented) boot_addr0 and boot_addr1.
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Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
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The @var{num} parameter is a value shown by @command{flash banks}.
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@end deffn
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@deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
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Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
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Warning: The meaning of the various bits depends on the device, always check datasheet!
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The @var{num} parameter is a value shown by @command{flash banks}, user_options a
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12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, boot_addr0 and boot_addr1
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two halfwords (of FLASH_OPTCR1).
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The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
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12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
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@var{boot_addr1} two halfwords (of FLASH_OPTCR1).
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@end deffn
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@deffn Command {stm32f2x optcr2_write} num optcr2
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Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
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The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
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@end deffn
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@end deffn
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@ -59,10 +59,14 @@
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*
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* Sector sizes in kiBytes:
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* 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
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* 1.5 MiByte part with 4 x 16, 1 x 64, 11 x 128.
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* 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
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* 1 MiByte STM32F42x/43x part with DB1M Option set:
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* 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
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*
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* STM32F7[2|3]
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* 512 kiByte part with 4 x 16, 1 x 64, 3 x 128.
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*
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* STM32F7[4|5]
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* 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
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*
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@ -93,6 +97,12 @@
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* RM0410
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* http://www.st.com/resource/en/reference_manual/dm00224583.pdf
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*
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* RM0430
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* http://www.st.com/resource/en/reference_manual/dm00305666.pdf
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*
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* RM0431
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* http://www.st.com/resource/en/reference_manual/dm00305990.pdf
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*
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* STM32F1x series - notice that this code was copy, pasted and knocked
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* into a stm32f2x driver, so in case something has been converted or
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* bugs haven't been fixed, here are the original manuals:
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@ -121,6 +131,7 @@
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#define STM32_FLASH_CR 0x40023c10
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#define STM32_FLASH_OPTCR 0x40023c14
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#define STM32_FLASH_OPTCR1 0x40023c18
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#define STM32_FLASH_OPTCR2 0x40023c1c
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/* FLASH_CR register bits */
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#define FLASH_PG (1 << 0)
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@ -152,6 +163,10 @@
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#define OPTCR_START (1 << 1)
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#define OPTCR_NDBANK (1 << 29) /* not dual bank mode */
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#define OPTCR_DB1M (1 << 30) /* 1 MiB devices dual flash bank option */
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#define OPTCR_SPRMOD (1 << 31) /* switches PCROPi/nWPRi interpretation */
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/* STM32_FLASH_OPTCR2 register bits */
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#define OPTCR2_PCROP_RDP (1 << 31) /* erase PCROP zone when decreasing RDP */
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/* register unlock keys */
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#define KEY1 0x45670123
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@ -166,14 +181,17 @@ struct stm32x_options {
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uint16_t user_options; /* bit 0-7 usual options, bit 8-11 extra options */
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uint32_t protection;
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uint32_t boot_addr;
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uint32_t optcr2_pcrop;
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};
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struct stm32x_flash_bank {
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struct stm32x_options option_bytes;
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int probed;
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bool has_large_mem; /* F42x/43x/469/479/7xx in dual bank mode */
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bool has_boot_addr; /* F7xx */
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bool has_extra_options; /* F42x/43x/469/479/7xx */
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bool has_boot_addr; /* F7xx */
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bool has_optcr2_pcrop; /* F72x/73x */
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int protection_bits; /* F413/423 */
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uint32_t user_bank_size;
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};
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@ -328,11 +346,13 @@ static int stm32x_read_options(struct flash_bank *bank)
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* whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
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stm32x_info->option_bytes.user_options = optiondata & 0xfc;
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stm32x_info->option_bytes.RDP = (optiondata >> 8) & 0xff;
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stm32x_info->option_bytes.protection = (optiondata >> 16) & 0xfff;
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stm32x_info->option_bytes.protection =
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(optiondata >> 16) & (~(0xffff << stm32x_info->protection_bits) & 0xffff);
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if (stm32x_info->has_extra_options) {
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/* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
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stm32x_info->option_bytes.user_options |= (optiondata >> 20) & 0xf00;
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stm32x_info->option_bytes.user_options |= (optiondata >> 20) &
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((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00);
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}
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if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
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@ -350,6 +370,20 @@ static int stm32x_read_options(struct flash_bank *bank)
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}
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}
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if (stm32x_info->has_optcr2_pcrop) {
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retval = target_read_u32(target, STM32_FLASH_OPTCR2, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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stm32x_info->option_bytes.optcr2_pcrop = optiondata;
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if (stm32x_info->has_optcr2_pcrop &&
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(stm32x_info->option_bytes.optcr2_pcrop & ~OPTCR2_PCROP_RDP)) {
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LOG_INFO("PCROP Engaged");
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}
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} else {
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stm32x_info->option_bytes.optcr2_pcrop = 0x0;
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}
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if (stm32x_info->option_bytes.RDP != 0xAA)
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LOG_INFO("Device Security Bit Set");
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@ -371,11 +405,13 @@ static int stm32x_write_options(struct flash_bank *bank)
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/* rebuild option data */
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optiondata = stm32x_info->option_bytes.user_options & 0xfc;
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optiondata |= stm32x_info->option_bytes.RDP << 8;
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optiondata |= (stm32x_info->option_bytes.protection & 0x0fff) << 16;
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optiondata |= (stm32x_info->option_bytes.protection &
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(~(0xffff << stm32x_info->protection_bits))) << 16;
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if (stm32x_info->has_extra_options) {
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/* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
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optiondata |= (stm32x_info->option_bytes.user_options & 0xf00) << 20;
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optiondata |= (stm32x_info->option_bytes.user_options &
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((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00)) << 20;
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}
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if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
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@ -392,6 +428,14 @@ static int stm32x_write_options(struct flash_bank *bank)
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return retval;
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}
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/* program extra pcrop register */
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if (stm32x_info->has_optcr2_pcrop) {
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retval = target_write_u32(target, STM32_FLASH_OPTCR2,
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stm32x_info->option_bytes.optcr2_pcrop);
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if (retval != ERROR_OK)
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return retval;
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}
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/* program options */
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retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata);
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if (retval != ERROR_OK)
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@ -418,6 +462,8 @@ static int stm32x_write_options(struct flash_bank *bank)
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static int stm32x_protect_check(struct flash_bank *bank)
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{
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struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
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struct flash_sector *prot_blocks;
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int num_prot_blocks;
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/* read write protection settings */
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int retval = stm32x_read_options(bank);
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@ -426,27 +472,18 @@ static int stm32x_protect_check(struct flash_bank *bank)
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return retval;
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}
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if (stm32x_info->has_boot_addr && stm32x_info->has_large_mem) {
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/* F76x/77x: bit k protects sectors 2*k and 2*k+1 */
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for (int i = 0; i < (bank->num_sectors >> 1); i++) {
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if (stm32x_info->option_bytes.protection & (1 << i)) {
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bank->sectors[i << 1].is_protected = 0;
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bank->sectors[(i << 1) + 1].is_protected = 0;
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if (bank->prot_blocks) {
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num_prot_blocks = bank->num_prot_blocks;
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prot_blocks = bank->prot_blocks;
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} else {
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bank->sectors[i << 1].is_protected = 1;
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bank->sectors[(i << 1) + 1].is_protected = 1;
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}
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}
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} else {
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/* one protection bit per sector */
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for (int i = 0; i < bank->num_sectors; i++) {
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if (stm32x_info->option_bytes.protection & (1 << i))
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bank->sectors[i].is_protected = 0;
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else
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bank->sectors[i].is_protected = 1;
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}
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num_prot_blocks = bank->num_sectors;
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prot_blocks = bank->sectors;
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}
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for (int i = 0; i < num_prot_blocks; i++)
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prot_blocks[i].is_protected =
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~(stm32x_info->option_bytes.protection >> i) & 1;
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return ERROR_OK;
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}
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@ -515,17 +552,6 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
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return retval;
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}
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if (stm32x_info->has_boot_addr && stm32x_info->has_large_mem) {
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/* F76x/77x: bit k protects sectors 2*k and 2*k+1 */
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if ((first & 1) != 0 || (last & 1) != 1) {
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LOG_ERROR("sector protection must be double sector aligned");
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return ERROR_FAIL;
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} else {
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first >>= 1;
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last >>= 1;
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}
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}
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for (int i = first; i <= last; i++) {
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if (set)
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stm32x_info->option_bytes.protection &= ~(1 << i);
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@ -829,7 +855,7 @@ static int stm32x_probe(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
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int i;
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int i, num_prot_blocks;
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uint16_t flash_size_in_kb;
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uint32_t flash_size_reg = 0x1FFF7A22;
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uint16_t max_sector_size_in_kb = 128;
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@ -841,15 +867,31 @@ static int stm32x_probe(struct flash_bank *bank)
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stm32x_info->has_large_mem = false;
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stm32x_info->has_boot_addr = false;
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stm32x_info->has_extra_options = false;
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stm32x_info->has_optcr2_pcrop = false;
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stm32x_info->protection_bits = 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
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num_prot_blocks = 0;
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if (bank->sectors) {
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free(bank->sectors);
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bank->num_sectors = 0;
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bank->sectors = NULL;
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}
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if (bank->prot_blocks) {
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free(bank->prot_blocks);
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bank->num_prot_blocks = 0;
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bank->prot_blocks = NULL;
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}
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/* read stm32 device id register */
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int retval = stm32x_get_device_id(bank, &device_id);
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if (retval != ERROR_OK)
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return retval;
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LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
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device_id &= 0xfff; /* only bits 0-11 are used further on */
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/* set max flash size depending on family, id taken from AN2606 */
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switch (device_id & 0xfff) {
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switch (device_id) {
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case 0x411: /* F20x/21x */
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case 0x413: /* F40x/41x */
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max_flash_size_in_kb = 1024;
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@ -892,6 +934,21 @@ static int stm32x_probe(struct flash_bank *bank)
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stm32x_info->has_boot_addr = true;
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break;
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case 0x452: /* F72x/73x */
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max_flash_size_in_kb = 512;
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flash_size_reg = 0x1FF07A22; /* yes, 0x1FF*0*7A22, not 0x1FF*F*7A22 */
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stm32x_info->has_extra_options = true;
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stm32x_info->has_boot_addr = true;
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stm32x_info->has_optcr2_pcrop = true;
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break;
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case 0x463: /* F413x/423x */
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max_flash_size_in_kb = 1536;
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stm32x_info->has_extra_options = true;
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stm32x_info->protection_bits = 15;
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num_prot_blocks = 15;
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break;
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default:
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LOG_WARNING("Cannot identify target as a STM32 family.");
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return ERROR_FAIL;
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@ -920,12 +977,8 @@ static int stm32x_probe(struct flash_bank *bank)
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/* did we assign flash size? */
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assert(flash_size_in_kb != 0xffff);
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/* Devices with > 1024 kiByte always are dual-banked */
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if (flash_size_in_kb > 1024)
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stm32x_info->has_large_mem = true;
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/* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
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if ((device_id & 0xfff) == 0x419 || (device_id & 0xfff) == 0x434) {
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if ((device_id == 0x419) || (device_id == 0x434)) {
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uint32_t optiondata;
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retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
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if (retval != ERROR_OK) {
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@ -942,7 +995,7 @@ static int stm32x_probe(struct flash_bank *bank)
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}
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/* F76x/77x devices have a dual bank option */
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if ((device_id & 0xfff) == 0x451) {
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if (device_id == 0x451) {
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uint32_t optiondata;
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retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
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if (retval != ERROR_OK) {
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@ -963,11 +1016,6 @@ static int stm32x_probe(struct flash_bank *bank)
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int num_pages = flash_size_in_kb / max_sector_size_in_kb
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+ (stm32x_info->has_large_mem ? 8 : 4);
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if (bank->sectors) {
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free(bank->sectors);
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bank->sectors = NULL;
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}
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bank->base = base_address;
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bank->num_sectors = num_pages;
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bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
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@ -978,15 +1026,44 @@ static int stm32x_probe(struct flash_bank *bank)
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bank->size = 0;
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LOG_DEBUG("allocated %d sectors", num_pages);
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/* F76x/77x in dual bank mode */
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if ((device_id == 0x451) && stm32x_info->has_large_mem)
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num_prot_blocks = num_pages >> 1;
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if (num_prot_blocks) {
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bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
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for (i = 0; i < num_prot_blocks; i++)
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bank->prot_blocks[i].is_protected = 0;
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LOG_DEBUG("allocated %d prot blocks", num_prot_blocks);
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}
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if (stm32x_info->has_large_mem) {
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/* dual-bank */
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setup_bank(bank, 0, flash_size_in_kb >> 1, max_sector_size_in_kb);
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setup_bank(bank, num_pages >> 1, flash_size_in_kb >> 1,
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max_sector_size_in_kb);
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/* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
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if (device_id == 0x451) {
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for (i = 0; i < num_prot_blocks; i++) {
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bank->prot_blocks[i].offset = bank->sectors[i << 1].offset;
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bank->prot_blocks[i].size = bank->sectors[i << 1].size << 1;
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}
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}
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} else {
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/* single-bank */
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setup_bank(bank, 0, flash_size_in_kb, max_sector_size_in_kb);
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/* F413/F423, sectors 14 and 15 share one common protection bit */
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if (device_id == 0x463) {
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for (i = 0; i < num_prot_blocks; i++) {
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bank->prot_blocks[i].offset = bank->sectors[i].offset;
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bank->prot_blocks[i].size = bank->sectors[i].size;
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}
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bank->prot_blocks[num_prot_blocks - 1].size <<= 1;
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}
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}
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bank->num_prot_blocks = num_prot_blocks;
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assert((bank->size >> 10) == flash_size_in_kb);
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stm32x_info->probed = 1;
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|
|
@ -1107,6 +1184,14 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
|
|||
case 0x1001:
|
||||
rev_str = "Z";
|
||||
break;
|
||||
|
||||
case 0x2000:
|
||||
rev_str = "B";
|
||||
break;
|
||||
|
||||
case 0x3000:
|
||||
rev_str = "C";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -1134,6 +1219,26 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
|
|||
}
|
||||
break;
|
||||
|
||||
case 0x452:
|
||||
device_str = "STM32F7[2|3]x";
|
||||
|
||||
switch (rev_id) {
|
||||
case 0x1000:
|
||||
rev_str = "A";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x463:
|
||||
device_str = "STM32F4[1|2]3";
|
||||
|
||||
switch (rev_id) {
|
||||
case 0x1000:
|
||||
rev_str = "A";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
snprintf(buf, buf_size, "Cannot identify target as a STM32F2/4/7\n");
|
||||
return ERROR_FAIL;
|
||||
|
|
@ -1164,8 +1269,8 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
|
|||
target = bank->target;
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
LOG_INFO("Target not halted");
|
||||
/* return ERROR_TARGET_NOT_HALTED; */
|
||||
}
|
||||
|
||||
if (stm32x_read_options(bank) != ERROR_OK) {
|
||||
|
|
@ -1203,8 +1308,8 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
|
|||
target = bank->target;
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
LOG_INFO("Target not halted");
|
||||
/* return ERROR_TARGET_NOT_HALTED; */
|
||||
}
|
||||
|
||||
if (stm32x_read_options(bank) != ERROR_OK) {
|
||||
|
|
@ -1215,6 +1320,9 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
|
|||
/* clear readout protection and complementary option bytes
|
||||
* this will also force a device unlock if set */
|
||||
stm32x_info->option_bytes.RDP = 0xAA;
|
||||
if (stm32x_info->has_optcr2_pcrop) {
|
||||
stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1 << bank->num_sectors);
|
||||
}
|
||||
|
||||
if (stm32x_write_options(bank) != ERROR_OK) {
|
||||
command_print(CMD_CTX, "%s failed to unlock device", bank->driver->name);
|
||||
|
|
@ -1327,8 +1435,12 @@ COMMAND_HANDLER(stm32f2x_handle_options_read_command)
|
|||
" boot_add0 0x%04X, boot_add1 0x%04X",
|
||||
stm32x_info->option_bytes.user_options,
|
||||
boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
|
||||
if (stm32x_info->has_optcr2_pcrop) {
|
||||
command_print(CMD_CTX, "stm32f2x optcr2_pcrop 0x%08X",
|
||||
stm32x_info->option_bytes.optcr2_pcrop);
|
||||
}
|
||||
} else {
|
||||
command_print(CMD_CTX, "stm32f2x user_options 0x%03X,",
|
||||
command_print(CMD_CTX, "stm32f2x user_options 0x%03X",
|
||||
stm32x_info->option_bytes.user_options);
|
||||
}
|
||||
} else {
|
||||
|
|
@ -1345,7 +1457,7 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command)
|
|||
int retval;
|
||||
struct flash_bank *bank;
|
||||
struct stm32x_flash_bank *stm32x_info = NULL;
|
||||
uint16_t user_options, boot_addr0, boot_addr1;
|
||||
uint16_t user_options, boot_addr0, boot_addr1, options_mask;
|
||||
|
||||
if (CMD_ARGC < 1) {
|
||||
command_print(CMD_CTX, "stm32f2x options_write <bank> ...");
|
||||
|
|
@ -1378,9 +1490,11 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command)
|
|||
}
|
||||
|
||||
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], user_options);
|
||||
if (user_options & (stm32x_info->has_extra_options ? ~0xffc : ~0xfc)) {
|
||||
options_mask = !stm32x_info->has_extra_options ? ~0xfc :
|
||||
~(((0xf00 << (stm32x_info->protection_bits - 12)) | 0xff) & 0xffc);
|
||||
if (user_options & options_mask) {
|
||||
command_print(CMD_CTX, "stm32f2x invalid user_options");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
stm32x_info->option_bytes.user_options = user_options;
|
||||
|
|
@ -1400,6 +1514,48 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command)
|
|||
return retval;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
|
||||
{
|
||||
int retval;
|
||||
struct flash_bank *bank;
|
||||
struct stm32x_flash_bank *stm32x_info = NULL;
|
||||
uint32_t optcr2_pcrop;
|
||||
|
||||
if (CMD_ARGC != 2) {
|
||||
command_print(CMD_CTX, "stm32f2x optcr2_write <bank> <optcr2_value>");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
stm32x_info = bank->driver_priv;
|
||||
if (!stm32x_info->has_optcr2_pcrop) {
|
||||
command_print(CMD_CTX, "no optcr2 register");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
command_print(CMD_CTX, "INFO: To disable PCROP, set PCROP_RDP"
|
||||
" with PCROPi bits STILL SET, then\nlock device and"
|
||||
" finally unlock it. Clears PCROP and mass erases flash.");
|
||||
|
||||
retval = stm32x_read_options(bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop);
|
||||
stm32x_info->option_bytes.optcr2_pcrop = optcr2_pcrop;
|
||||
|
||||
if (stm32x_write_options(bank) != ERROR_OK) {
|
||||
command_print(CMD_CTX, "stm32f2x failed to write options");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
command_print(CMD_CTX, "stm32f2x optcr2_write complete.");
|
||||
return retval;
|
||||
}
|
||||
|
||||
static const struct command_registration stm32x_exec_command_handlers[] = {
|
||||
{
|
||||
.name = "lock",
|
||||
|
|
@ -1433,9 +1589,17 @@ static const struct command_registration stm32x_exec_command_handlers[] = {
|
|||
.name = "options_write",
|
||||
.handler = stm32f2x_handle_options_write_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.usage = "bank_id user_options [ boot_add0 boot_add1]",
|
||||
.usage = "bank_id user_options [ boot_add0 boot_add1 ]",
|
||||
.help = "Write option bytes",
|
||||
},
|
||||
{
|
||||
.name = "optcr2_write",
|
||||
.handler = stm32f2x_handle_optcr2_write_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.usage = "bank_id optcr2",
|
||||
.help = "Write optcr2 word",
|
||||
},
|
||||
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue