John McCarthy <jgmcc@magma.ca> adds support for DMA mode access as supported by EJTAG 1.0/2.0 processors
git-svn-id: svn://svn.berlios.de/openocd/trunk@1029 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
oharboe
parent
eadd49bef0
commit
76be215ee1
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@ -13,11 +13,11 @@ libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c
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arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
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arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_swjdp.c \
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etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
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mips32_pracc.c mips_ejtag.c
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mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
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noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
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arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
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arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \
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etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h
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etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
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nobase_dist_pkglib_DATA = xscale/debug_handler.bin target/at91eb40a.cfg \
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event/at91r40008_reset.script event/sam7x256_reset.script \
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@ -0,0 +1,441 @@
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/***************************************************************************
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* Copyright (C) 2008 by John McCarthy *
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* jgmcc@magma.ca *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <string.h>
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#include "log.h"
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#include "mips32.h"
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#include "mips32_dmaacc.h"
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/*
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* The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
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* to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
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* (and any others that support EJTAG DMA transfers).
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* Note: This only supports memory read/write. Since the BCM5352 doesn't
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* appear to support PRACC accesses, all debug functions except halt
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* do not work. Still, this does allow erasing/writing flash as well as
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* displaying/modifying memory and memory mapped registers.
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*/
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static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
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{
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u32 v;
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u32 ctrl_reg;
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int retries = RETRY_ATTEMPTS;
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begin_ejtag_dma_read:
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// Setup Address
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Read & set DSTRT
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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// Wait for DSTRT to Clear
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do {
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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} while(ctrl_reg & EJTAG_CTRL_DSTRT);
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// Read Data
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, data);
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// Clear DMA & Check DERR
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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if (ctrl_reg & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
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goto begin_ejtag_dma_read;
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} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
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{
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u32 v;
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u32 ctrl_reg;
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int retries = RETRY_ATTEMPTS;
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begin_ejtag_dma_read_h:
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// Setup Address
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Read & set DSTRT
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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// Wait for DSTRT to Clear
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do {
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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} while(ctrl_reg & EJTAG_CTRL_DSTRT);
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// Read Data
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Clear DMA & Check DERR
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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if (ctrl_reg & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
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goto begin_ejtag_dma_read_h;
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} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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// Handle the bigendian/littleendian
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if ( addr & 0x2 ) *data = (v>>16)&0xffff ;
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else *data = (v&0x0000ffff) ;
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return ERROR_OK;
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}
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static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
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{
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u32 v;
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u32 ctrl_reg;
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int retries = RETRY_ATTEMPTS;
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begin_ejtag_dma_read_b:
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// Setup Address
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Read & set DSTRT
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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// Wait for DSTRT to Clear
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do {
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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} while(ctrl_reg & EJTAG_CTRL_DSTRT);
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// Read Data
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Clear DMA & Check DERR
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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if (ctrl_reg & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
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goto begin_ejtag_dma_read_b;
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} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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// Handle the bigendian/littleendian
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switch(addr & 0x3) {
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case 0: *data = v & 0xff; break;
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case 1: *data = (v>>8) & 0xff; break;
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case 2: *data = (v>>16) & 0xff; break;
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case 3: *data = (v>>24) & 0xff; break;
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}
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return ERROR_OK;
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}
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static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
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{
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u32 v;
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u32 ctrl_reg;
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int retries = RETRY_ATTEMPTS;
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begin_ejtag_dma_write:
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// Setup Address
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Setup Data
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v = data;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Write & set DSTRT
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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// Wait for DSTRT to Clear
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do {
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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} while(ctrl_reg & EJTAG_CTRL_DSTRT);
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// Clear DMA & Check DERR
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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if (ctrl_reg & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
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goto begin_ejtag_dma_write;
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} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
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{
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u32 v;
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u32 ctrl_reg;
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int retries = RETRY_ATTEMPTS;
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// Handle the bigendian/littleendian
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data &= 0xffff;
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data |= data<<16;
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begin_ejtag_dma_write_h:
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// Setup Address
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Setup Data
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v = data;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Write & set DSTRT
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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// Wait for DSTRT to Clear
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do {
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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} while(ctrl_reg & EJTAG_CTRL_DSTRT);
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// Clear DMA & Check DERR
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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if (ctrl_reg & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
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goto begin_ejtag_dma_write_h;
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} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
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{
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u32 v;
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u32 ctrl_reg;
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int retries = RETRY_ATTEMPTS;
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// Handle the bigendian/littleendian
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data &= 0xff;
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data |= data<<8;
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data |= data<<16;
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begin_ejtag_dma_write_b:
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// Setup Address
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Setup Data
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v = data;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
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mips_ejtag_drscan_32(ejtag_info, &v);
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// Initiate DMA Write & set DSTRT
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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// Wait for DSTRT to Clear
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do {
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ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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} while(ctrl_reg & EJTAG_CTRL_DSTRT);
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// Clear DMA & Check DERR
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
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mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
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if (ctrl_reg & EJTAG_CTRL_DERR)
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{
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if (retries--) {
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printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
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goto begin_ejtag_dma_write_b;
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} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
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{
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switch (size)
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{
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case 1:
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return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf);
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case 2:
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return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);
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case 4:
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return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);
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}
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return ERROR_OK;
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}
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int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
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{
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int i;
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int retval;
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for(i=0; i<count; i++) {
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if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
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{
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int i;
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int retval;
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for(i=0; i<count; i++) {
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if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
|
||||
|
||||
int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
|
||||
{
|
||||
int i;
|
||||
int retval;
|
||||
|
||||
for(i=0; i<count; i++) {
|
||||
if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
|
||||
{
|
||||
switch (size)
|
||||
{
|
||||
case 1:
|
||||
return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf);
|
||||
case 2:
|
||||
return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);
|
||||
case 4:
|
||||
return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
|
||||
{
|
||||
int i;
|
||||
int retval;
|
||||
|
||||
for(i=0; i<count; i++) {
|
||||
if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
|
||||
{
|
||||
int i;
|
||||
int retval;
|
||||
|
||||
for(i=0; i<count; i++) {
|
||||
if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
|
||||
{
|
||||
int i;
|
||||
int retval;
|
||||
|
||||
for(i=0; i<count; i++) {
|
||||
if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2008 by John McCarthy *
|
||||
* jgmcc@magma.ca *
|
||||
* *
|
||||
* Copyright (C) 2008 by Spencer Oliver *
|
||||
* spen@spen-soft.co.uk *
|
||||
* *
|
||||
* Copyright (C) 2008 by David T.L. Wong *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
#ifndef MIPS32_DMAACC_H
|
||||
#define MIPS32_DMAACC_H
|
||||
|
||||
#include "mips_ejtag.h"
|
||||
|
||||
#define EJTAG_CTRL_DMA_BYTE 0x00000000
|
||||
#define EJTAG_CTRL_DMA_HALFWORD 0x00000080
|
||||
#define EJTAG_CTRL_DMA_WORD 0x00000100
|
||||
#define EJTAG_CTRL_DMA_TRIPLEBYTE 0x00000180
|
||||
|
||||
#define RETRY_ATTEMPTS 4
|
||||
|
||||
extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
|
||||
extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
|
||||
|
||||
extern int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);
|
||||
extern int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
|
||||
extern int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
|
||||
|
||||
extern int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);
|
||||
extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
|
||||
extern int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
|
||||
|
||||
#if 0
|
||||
extern int mips32_dmaacc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs);
|
||||
extern int mips32_dmaacc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -204,6 +204,9 @@ int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
|
|||
/* break bit will be cleared by hardware */
|
||||
ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
|
||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
|
||||
LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_info->ejtag_ctrl);
|
||||
if((ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
|
||||
LOG_DEBUG("Failed to enter Debug Mode!");
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -275,6 +278,17 @@ int mips_ejtag_init(mips_ejtag_t *ejtag_info)
|
|||
LOG_DEBUG("EJTAG: Unknown Version Detected");
|
||||
break;
|
||||
}
|
||||
LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
|
||||
ejtag_info->impcode & (1<<28) ? " R3k": " R4k",
|
||||
ejtag_info->impcode & (1<<24) ? " DINT": "",
|
||||
ejtag_info->impcode & (1<<22) ? " ASID_8": "",
|
||||
ejtag_info->impcode & (1<<21) ? " ASID_6": "",
|
||||
ejtag_info->impcode & (1<<16) ? " MIPS16": "",
|
||||
ejtag_info->impcode & (1<<14) ? " noDMA": " DMA",
|
||||
ejtag_info->impcode & (1<<0) ? " MIPS64": " MIPS32"
|
||||
);
|
||||
if((ejtag_info->impcode & (1<<14)) == 0)
|
||||
LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
|
||||
|
||||
/* set initial state for ejtag control reg */
|
||||
ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
#define EJTAG_INST_TCBCONTROLA 0x10
|
||||
#define EJTAG_INST_TCBCONTROLB 0x11
|
||||
#define EJTAG_INST_TCBDATA 0x12
|
||||
#define EJTAG_INST_BYPASS 0x1F
|
||||
#define EJTAG_INST_BYPASS 0xFF
|
||||
|
||||
#define EJTAG_CTRL_TOF (1 << 1)
|
||||
#define EJTAG_CTRL_TIF (1 << 2)
|
||||
|
|
|
|||
|
|
@ -512,7 +512,11 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou
|
|||
case 4:
|
||||
case 2:
|
||||
case 1:
|
||||
return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
/* if noDMA off, use DMAACC mode for memory read */
|
||||
if(ejtag_info->impcode & (1<<14))
|
||||
return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
else
|
||||
return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
default:
|
||||
LOG_ERROR("BUG: we shouldn't get here");
|
||||
exit(-1);
|
||||
|
|
@ -547,7 +551,11 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co
|
|||
case 4:
|
||||
case 2:
|
||||
case 1:
|
||||
mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
/* if noDMA off, use DMAACC mode for memory write */
|
||||
if(ejtag_info->impcode & (1<<14))
|
||||
mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
else
|
||||
mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("BUG: we shouldn't get here");
|
||||
|
|
|
|||
Loading…
Reference in New Issue