added at91sam9260.cfg, nslu2.cfg, pxa255.cfg, pxa255_sst.cfg
zy1000.cfg git-svn-id: svn://svn.berlios.de/openocd/trunk@435 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
oharboe
parent
fe20b12fbd
commit
75e69503b9
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@ -5,6 +5,7 @@ AC_SEARCH_LIBS([ioperm], [ioperm])
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AC_CANONICAL_HOST
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AC_CANONICAL_HOST
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AC_CHECK_HEADERS(jtag_minidriver.h)
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AC_CHECK_HEADERS(sys/param.h)
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AC_CHECK_HEADERS(sys/param.h)
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AC_CHECK_HEADERS(elf.h)
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AC_CHECK_HEADERS(elf.h)
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@ -22,6 +22,8 @@ noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7t
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nobase_dist_pkglib_DATA = xscale/debug_handler.bin event/at91eb40a_reset.script target/at91eb40a.cfg \
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nobase_dist_pkglib_DATA = xscale/debug_handler.bin event/at91eb40a_reset.script target/at91eb40a.cfg \
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event/at91r40008_reset.script event/sam7s256_reset.script event/sam7x256_reset.script \
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event/at91r40008_reset.script event/sam7s256_reset.script event/sam7x256_reset.script \
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target/at91r40008.cfg target/lpc2148.cfg target/lpc2294.cfg target/sam7s256.cfg \
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target/at91r40008.cfg target/lpc2148.cfg target/lpc2294.cfg target/sam7s256.cfg \
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target/sam7x256.cfg target/str710.cfg target/str912.cfg
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target/sam7x256.cfg target/str710.cfg target/str912.cfg target/nslu2.cfg target/pxa255_sst.cfg \
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target/pxa255.cfg target/zy1000.cfg event/zy1000_reset.script event/at91sam9260_reset.script target/at91sam9260.cfg
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@ -0,0 +1,58 @@
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mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
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mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
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mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
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sleep 10 # wait 10 ms
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mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
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sleep 10 # wait 10 ms
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mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
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sleep 10 # wait 10 ms
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jtag_speed 0 # Increase JTAG Speed to 6 MHz
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arm7_9 dcc_downloads enable # Enable faster DCC downloads
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mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
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mww 0xffffec04 0x09070806 # SMC_PULSE0
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mww 0xffffec08 0x000d000b # SMC_CYCLE0
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mww 0xffffec0c 0x00001003 # SMC_MODE0
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flash probe 0 # Identify flash bank 0
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mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
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mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
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mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
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#mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
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mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
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mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
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mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
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mww 0x20000000 0
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mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
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@ -0,0 +1,18 @@
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reg cpsr 0x000000D3
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mww 0xFFE00000 0x0100273D
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mww 0xFFE00004 0x08002125
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mww 0xFFEe0008 0x02002125
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mww 0xFFE0000c 0x03002125
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mww 0xFFE00010 0x40000000
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mww 0xFFE00014 0x50000000
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mww 0xFFE00018 0x60000000
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mww 0xFFE0001c 0x70000000
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mww 0xFFE00020 0x00000001
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mww 0xFFE00024 0x00000000
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mww 0xFFFFF124 0xFFFFFFFF
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mww 0xffff0010 0x100
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mww 0xffff0034 0x100
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@ -0,0 +1,33 @@
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# Thanks to Pieter Conradie for this script!
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# Target: Atmel AT91SAM9260
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######################################
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reset_config trst_and_srst
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#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
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jtag_device 4 0x1 0xf 0xe
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jtag_nsrst_delay 200
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jtag_ntrst_delay 0
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######################
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# Target configuration
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######################
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#target <type> <endianess> <reset mode> <JTAG pos> <variant>
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target arm926ejs little reset_init 0 arm926ejs
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target_script 0 reset event/at91sam9260_reset.script
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run_and_halt_time 0 30
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#working area <target#> <address> <size> <backup|nobackup>
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working_area 0 0x00300000 0x1000 backup
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#####################
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# Flash configuration
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#####################
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#flash bank cfi <base> <size> <chip width> <bus width> <target#>
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flash bank cfi 0x10000000 0x01000000 2 2 0
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@ -0,0 +1,22 @@
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# use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config srst_only
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# jtag scan chain
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#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
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jtag_device 7 0x1 0x7f 0x7e
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# target configuration
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target xscale big reset_init 0 ixp42x
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run_and_halt_time 0 30
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# maps to PXA internal RAM. If you are using a PXA255
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# you must initialize SDRAM or leave this option off
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working_area 0 0x00020000 0x10000 nobackup
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# flash bank <driver> <base> <size> <chip_width> <bus_width>
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#flash bank cfi 0x50000000 0x1000000 2 4 0
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@ -0,0 +1,86 @@
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jtag_device 5 0x1 0x1f 0x1e
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jtag_nsrst_delay 200
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jtag_ntrst_delay 200
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target xscale little reset_init 0 pxa255
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reset_config trst_and_srst
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run_and_halt_time 0 30
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target_script 0 reset /ram/pxa255.init
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#xscale debug_handler 0 0xFFFF0800 # debug handler base address
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trunc /ram/pxa255.init
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append /ram/pxa255.init #configuration file for PXA250 Evaluation Board
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append /ram/pxa255.init # -----------------------------------------------------
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append /ram/pxa255.init #
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append /ram/pxa255.init xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
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append /ram/pxa255.init #
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append /ram/pxa255.init # setup GPIO
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append /ram/pxa255.init #
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append /ram/pxa255.init mww 0x40E00018 0x00008000 #CPSR0
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E0001C 0x00000002 #GPSR1
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E00020 0x00000008 #GPSR2
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E0000C 0x00008000 #GPDR0
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E00054 0x80000000 #GAFR0_L
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E00058 0x00188010 #GAFR0_H
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E0005C 0x60908018 #GAFR1_L
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E0000C 0x0280E000 #GPDR0
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E00010 0x821C88B2 #GPDR1
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E00014 0x000F03DB #GPDR2
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x40E00000 0x000F03DB #GPLR0
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init
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append /ram/pxa255.init
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append /ram/pxa255.init mww 0x40F00004 0x00000020 #PSSR
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init
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append /ram/pxa255.init #
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append /ram/pxa255.init # setup memory controller
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append /ram/pxa255.init #
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append /ram/pxa255.init mww 0x48000008 0x01111998 #MSC0
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000010 0x00047ff0 #MSC2
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000014 0x00000000 #MECR
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000028 0x00010504 #MCMEM0
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x4800002C 0x00010504 #MCMEM1
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000030 0x00010504 #MCATT0
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000034 0x00010504 #MCATT1
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000038 0x00004715 #MCIO0
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x4800003C 0x00004715 #MCIO1
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init #
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append /ram/pxa255.init mww 0x48000004 0x03CA4018 #MDREF
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000004 0x004B4018 #MDREF
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000004 0x000B4018 #MDREF
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000004 0x000BC018 #MDREF
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000000 0x00001AC8 #MDCNFG
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init
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append /ram/pxa255.init mww 0x48000000 0x00001AC9 #MDCNFG
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init mww 0x48000040 0x00000000 #MDMRS
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append /ram/pxa255.init sleep 20
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append /ram/pxa255.init
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@ -0,0 +1,13 @@
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# A PXA255 test board with SST 39LF400A flash
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#
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# At reset the memory map is as follows. Note that
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# the memory map changes later on as the application
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# starts...
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#
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# RAM at 0x40000000
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# Flash at 0x00000000
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#
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script /target/pxa255.cfg
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# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
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flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
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working_area 0 0x4000000 0x4000 nobackup 0
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@ -0,0 +1,30 @@
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#Script for ZY1000
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#Atmel ties SRST & TRST together, at which point it makes
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#no sense to use TRST, but use TMS instead.
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#
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#The annoying thing with tying SRST & TRST together is that
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#there is no way to halt the CPU *before and during* the
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#SRST reset, which means that the CPU will run a number
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#of cycles before it can be halted(as much as milliseconds).
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reset_config srst_only srst_pulls_trst
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#jtag scan chain
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#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
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jtag_device 4 0x1 0xf 0xe
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#target configuration
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#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
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target arm7tdmi little reset_init 0 arm7tdmi-s_r4
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# at CPU CLK <32kHz this must be disabled
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arm7 fast_memory_access enable
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arm7_9 dcc_downloads enable
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flash bank ecosflash 0x01000000 0x200000 2 2 0 /rom/at91eb40a.elf
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target_script 0 reset event/zy1000_reset.script
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# required for usable performance. Used for lots of
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# other things than flash programming.
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working_area 0 0x00000000 0x20000 nobackup
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Loading…
Reference in New Issue