reg_cache_t -> struct reg_cache

Remove misleading typedef and redundant suffix from struct reg_cache.

src/target/arm11.c

@@ -1933,7 +1933,7 @@ static int arm11_build_reg_cache(target_t *target)
 {
 	struct arm11_common *arm11 = target->arch_info;
 
-	NEW(reg_cache_t,		cache,				1);
+	NEW(struct reg_cache,		cache,				1);
 	NEW(reg_t,				reg_list,			ARM11_REGCACHE_COUNT);
 	NEW(struct arm11_reg_state,	arm11_reg_states,	ARM11_REGCACHE_COUNT);
 
@@ -1951,7 +1951,7 @@ static int arm11_build_reg_cache(target_t *target)
 	cache->reg_list	= reg_list;
 	cache->num_regs	= ARM11_REGCACHE_COUNT;
 
-	reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	(*cache_p) = cache;
 
 	arm11->core_cache = cache;

src/target/arm11.h

@@ -116,7 +116,7 @@ struct arm11_common
 	size_t	free_wrps;				/**< keep track of breakpoints allocated by arm11_add_watchpoint() */
 
 	// GA
-	reg_cache_t *core_cache;
+	struct reg_cache *core_cache;
 };
 
 

src/target/arm7_9_common.h

@@ -43,7 +43,7 @@ struct arm7_9_common
 	uint32_t common_magic;
 
 	struct arm_jtag jtag_info; /**< JTAG information for target */
-	reg_cache_t *eice_cache; /**< Embedded ICE register cache */
+	struct reg_cache *eice_cache; /**< Embedded ICE register cache */
 
 	uint32_t arm_bkpt; /**< ARM breakpoint instruction */
 	uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */

src/target/arm7tdmi.c

@@ -639,7 +639,7 @@ static void arm7tdmi_branch_resume_thumb(target_t *target)
 
 static void arm7tdmi_build_reg_cache(target_t *target)
 {
-	reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
@@ -655,8 +655,8 @@ int arm7tdmi_examine(struct target_s *target)
 	if (!target_was_examined(target))
 	{
 		/* get pointers to arch-specific information */
-		reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+		struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-		reg_cache_t *t = embeddedice_build_reg_cache(target, arm7_9);
+		struct reg_cache *t = embeddedice_build_reg_cache(target, arm7_9);
 		if (t == NULL)
 			return ERROR_FAIL;
 

src/target/arm9tdmi.c

@@ -735,7 +735,7 @@ void arm9tdmi_disable_single_step(target_t *target)
 
 static void arm9tdmi_build_reg_cache(target_t *target)
 {
-	reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
@@ -749,8 +749,8 @@ int arm9tdmi_examine(struct target_s *target)
 
 	if (!target_was_examined(target))
 	{
-		reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+		struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-		reg_cache_t *t;
+		struct reg_cache *t;
 		/* one extra register (vector catch) */
 		t = embeddedice_build_reg_cache(target, arm7_9);
 		if (t == NULL)

src/target/armv4_5.c

@@ -249,10 +249,10 @@ int armv4_5_invalidate_core_regs(target_t *target)
 	return ERROR_OK;
 }
 
-reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
+struct reg_cache* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
 {
 	int num_regs = 37;
-	reg_cache_t *cache = malloc(sizeof(reg_cache_t));
+	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 	reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 	struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
 	int i;

src/target/armv4_5.h

@@ -87,7 +87,7 @@ enum
 typedef struct arm
 {
 	int common_magic;
-	reg_cache_t *core_cache;
+	struct reg_cache *core_cache;
 
 	int /* armv4_5_mode */ core_mode;
 	enum armv4_5_state core_state;
@@ -135,7 +135,7 @@ struct armv4_5_core_reg
 	armv4_5_common_t *armv4_5_common;
 };
 
-reg_cache_t* armv4_5_build_reg_cache(target_t *target,
+struct reg_cache* armv4_5_build_reg_cache(target_t *target,
 		armv4_5_common_t *armv4_5_common);
 
 /* map psr mode bits to linear number */

src/target/armv7a.h

@@ -92,7 +92,7 @@ enum
 struct armv7a_common
 {
 	int common_magic;
-	reg_cache_t *core_cache;
+	struct reg_cache *core_cache;
 	enum armv7a_mode core_mode;
 	enum armv7a_state core_state;
 
@@ -150,7 +150,7 @@ struct armv7a_core_reg
 };
 
 int armv7a_arch_state(struct target_s *target);
-reg_cache_t *armv7a_build_reg_cache(target_t *target,
+struct reg_cache *armv7a_build_reg_cache(target_t *target,
 		struct armv7a_common *armv7a_common);
 int armv7a_register_commands(struct command_context_s *cmd_ctx);
 int armv7a_init_arch_info(target_t *target, struct armv7a_common *armv7a);

src/target/armv7m.c

@@ -524,12 +524,12 @@ int armv7m_arch_state(struct target_s *target)
 }
 
 /** Builds cache of architecturally defined registers.  */
-reg_cache_t *armv7m_build_reg_cache(target_t *target)
+struct reg_cache *armv7m_build_reg_cache(target_t *target)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	int num_regs = ARMV7M_NUM_REGS;
-	reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-	reg_cache_t *cache = malloc(sizeof(reg_cache_t));
+	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 	reg_t *reg_list = calloc(num_regs, sizeof(reg_t));
 	struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
 	int i;

src/target/armv7m.h

@@ -94,7 +94,7 @@ enum
 struct armv7m_common
 {
 	int common_magic;
-	reg_cache_t *core_cache;
+	struct reg_cache *core_cache;
 	enum armv7m_mode core_mode;
 	int exception_number;
 	struct swjdp_common swjdp_info;
@@ -134,7 +134,7 @@ struct armv7m_core_reg
 	struct armv7m_common *armv7m_common;
 };
 
-reg_cache_t *armv7m_build_reg_cache(target_t *target);
+struct reg_cache *armv7m_build_reg_cache(target_t *target);
 enum armv7m_mode armv7m_number_to_mode(int number);
 int armv7m_mode_to_number(enum armv7m_mode mode);
 

src/target/cortex_a8.c

@@ -1435,7 +1435,7 @@ static int cortex_a8_examine(struct target_s *target)
 
 static void cortex_a8_build_reg_cache(target_t *target)
 {
-	reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);

src/target/cortex_m3.c

@@ -1516,7 +1516,7 @@ static void
 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target_s *target)
 {
 	uint32_t dwtcr;
-	struct reg_cache_s *cache;
+	struct reg_cache *cache;
 	cortex_m3_dwt_comparator_t *comparator;
 	int reg, i;
 

src/target/cortex_m3.h

@@ -158,7 +158,7 @@ struct cortex_m3_common
 	int dwt_num_comp;
 	int dwt_comp_available;
 	cortex_m3_dwt_comparator_t *dwt_comparator_list;
-	struct reg_cache_s *dwt_cache;
+	struct reg_cache *dwt_cache;
 
 	struct armv7m_common armv7m;
 };

src/target/embeddedice.c

@@ -163,11 +163,11 @@ static int embeddedice_get_reg(reg_t *reg)
  * Different versions of the modules have different capabilities, such as
  * hardware support for vector_catch, single stepping, and monitor mode.
  */
-reg_cache_t *
+struct reg_cache *
 embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9)
 {
 	int retval;
-	reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
+	struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 	reg_t *reg_list = NULL;
 	struct embeddedice_reg *arch_info = NULL;
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;

src/target/embeddedice.h

@@ -93,7 +93,7 @@ struct embeddedice_reg
 	struct arm_jtag *jtag_info;
 };
 
-reg_cache_t* embeddedice_build_reg_cache(target_t *target,
+struct reg_cache* embeddedice_build_reg_cache(target_t *target,
 		struct arm7_9_common *arm7_9);
 
 int embeddedice_setup(target_t *target);

src/target/etb.c

@@ -121,9 +121,9 @@ static int etb_get_reg(reg_t *reg)
 	return ERROR_OK;
 }
 
-reg_cache_t* etb_build_reg_cache(etb_t *etb)
+struct reg_cache* etb_build_reg_cache(etb_t *etb)
 {
-	reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
+	struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 	reg_t *reg_list = NULL;
 	struct etb_reg *arch_info = NULL;
 	int num_regs = 9;

src/target/etb.h

@@ -39,7 +39,7 @@ typedef struct etb_s
 	etm_context_t *etm_ctx;
 	struct jtag_tap *tap;
 	uint32_t cur_scan_chain;
-	reg_cache_t *reg_cache;
+	struct reg_cache *reg_cache;
 
 	/* ETB parameters */
 	uint32_t ram_depth;
@@ -54,6 +54,6 @@ struct etb_reg
 
 extern struct etm_capture_driver etb_capture_driver;
 
-reg_cache_t* etb_build_reg_cache(etb_t *etb);
+struct reg_cache* etb_build_reg_cache(etb_t *etb);
 
 #endif /* ETB_H */

src/target/etm.c

@@ -231,7 +231,7 @@ static command_t *etm_cmd;
  */
 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
 {
-	reg_cache_t *cache = etm_ctx->reg_cache;
+	struct reg_cache *cache = etm_ctx->reg_cache;
 	int i;
 
 	for (i = 0; i < cache->num_regs; i++) {
@@ -248,7 +248,7 @@ static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
 }
 
 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
-		reg_cache_t *cache, struct etm_reg *ereg,
+		struct reg_cache *cache, struct etm_reg *ereg,
 		const struct etm_reg_info *r, unsigned nreg)
 {
 	reg_t *reg = cache->reg_list;
@@ -279,10 +279,10 @@ static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
 	}
 }
 
-reg_cache_t *etm_build_reg_cache(target_t *target,
+struct reg_cache *etm_build_reg_cache(target_t *target,
 		struct arm_jtag *jtag_info, etm_context_t *etm_ctx)
 {
-	reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
+	struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 	reg_t *reg_list = NULL;
 	struct etm_reg *arch_info = NULL;
 	unsigned bcd_vers, config;

src/target/etm.h

@@ -155,7 +155,7 @@ struct etmv1_trace_data
 typedef struct etm
 {
 	target_t *target;		/* target this ETM is connected to */
-	reg_cache_t *reg_cache;		/* ETM register cache */
+	struct reg_cache *reg_cache;		/* ETM register cache */
 	struct etm_capture_driver *capture_driver;	/* driver used to access ETM data */
 	void *capture_driver_priv;	/* capture driver private data */
 	uint32_t trigger_percent;	/* how much trace buffer to fill after trigger */
@@ -207,7 +207,7 @@ typedef enum
 	BR_RSVD7   = 0x7, /* reserved */
 } etmv1_branch_reason_t;
 
-reg_cache_t* etm_build_reg_cache(target_t *target,
+struct reg_cache* etm_build_reg_cache(target_t *target,
 		struct arm_jtag *jtag_info, etm_context_t *etm_ctx);
 
 int etm_setup(target_t *target);

src/target/mips32.c

@@ -271,14 +271,14 @@ int mips32_arch_state(struct target_s *target)
 	return ERROR_OK;
 }
 
-reg_cache_t *mips32_build_reg_cache(target_t *target)
+struct reg_cache *mips32_build_reg_cache(target_t *target)
 {
 	/* get pointers to arch-specific information */
 	struct mips32_common *mips32 = target->arch_info;
 
 	int num_regs = MIPS32NUMCOREREGS;
-	reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-	reg_cache_t *cache = malloc(sizeof(reg_cache_t));
+	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 	reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 	struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
 	int i;

src/target/mips32.h

@@ -49,7 +49,7 @@ struct mips32_common
 {
 	uint32_t common_magic;
 	void *arch_info;
-	reg_cache_t *core_cache;
+	struct reg_cache *core_cache;
 	struct mips_ejtag ejtag_info;
 	uint32_t core_regs[MIPS32NUMCOREREGS];
 
@@ -132,7 +132,7 @@ int mips32_init_arch_info(target_t *target,
 int mips32_restore_context(target_t *target);
 int mips32_save_context(target_t *target);
 
-reg_cache_t *mips32_build_reg_cache(target_t *target);
+struct reg_cache *mips32_build_reg_cache(target_t *target);
 
 int mips32_run_algorithm(struct target_s *target,
 		int num_mem_params, struct mem_param *mem_params,

src/target/register.c

@@ -30,11 +30,11 @@
 
 reg_arch_type_t *reg_arch_types = NULL;
 
-reg_t* register_get_by_name(reg_cache_t *first,
+reg_t* register_get_by_name(struct reg_cache *first,
 		const char *name, bool search_all)
 {
 	int i;
-	reg_cache_t *cache = first;
+	struct reg_cache *cache = first;
 
 	while (cache)
 	{
@@ -53,9 +53,9 @@ reg_t* register_get_by_name(reg_cache_t *first,
 	return NULL;
 }
 
-reg_cache_t** register_get_last_cache_p(reg_cache_t **first)
+struct reg_cache** register_get_last_cache_p(struct reg_cache **first)
 {
-	reg_cache_t **cache_p = first;
+	struct reg_cache **cache_p = first;
 
 	if (*cache_p)
 		while (*cache_p)

src/target/register.h

@@ -46,13 +46,13 @@ typedef struct reg_s
 	int arch_type;
 } reg_t;
 
-typedef struct reg_cache_s
+struct reg_cache
 {
 	char *name;
-	struct reg_cache_s *next;
+	struct reg_cache *next;
 	reg_t *reg_list;
 	int num_regs;
-} reg_cache_t;
+};
 
 typedef struct reg_arch_type_s
 {
@@ -62,9 +62,9 @@ typedef struct reg_arch_type_s
 	struct reg_arch_type_s *next;
 } reg_arch_type_t;
 
-reg_t* register_get_by_name(reg_cache_t *first,
+reg_t* register_get_by_name(struct reg_cache *first,
 		const char *name, bool search_all);
-reg_cache_t** register_get_last_cache_p(reg_cache_t **first);
+struct reg_cache** register_get_last_cache_p(struct reg_cache **first);
 
 int register_reg_arch_type(int (*get)(reg_t *reg),
 		int (*set)(reg_t *reg, uint8_t *buf));

src/target/target.c

@@ -1876,7 +1876,7 @@ COMMAND_HANDLER(handle_reg_command)
 	/* list all available registers for the current target */
 	if (argc == 0)
 	{
-		reg_cache_t *cache = target->reg_cache;
+		struct reg_cache *cache = target->reg_cache;
 
 		count = 0;
 		while (cache)
@@ -1919,7 +1919,7 @@ COMMAND_HANDLER(handle_reg_command)
 		unsigned num;
 		COMMAND_PARSE_NUMBER(uint, args[0], num);
 
-		reg_cache_t *cache = target->reg_cache;
+		struct reg_cache *cache = target->reg_cache;
 		count = 0;
 		while (cache)
 		{

src/target/target.h

@@ -154,7 +154,7 @@ typedef struct target_s
 	enum target_endianess endianness;	/* target endianess */
 	// also see: target_state_name()
 	enum target_state state;			/* the current backend-state (running, halted, ...) */
-	struct reg_cache_s *reg_cache;		/* the first register cache of the target (core regs) */
+	struct reg_cache *reg_cache;		/* the first register cache of the target (core regs) */
 	struct breakpoint_s *breakpoints;	/* list of breakpoints */
 	struct watchpoint *watchpoints;	/* list of watchpoints */
 	struct trace_s *trace_info;			/* generic trace information */

src/target/xscale.c

@@ -2821,7 +2821,7 @@ static void xscale_build_reg_cache(target_t *target)
 {
 	struct xscale_common_s *xscale = target_to_xscale(target);
 	struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
-	reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	xscale_reg_t *arch_info = malloc(sizeof(xscale_reg_arch_info));
 	int i;
 	int num_regs = sizeof(xscale_reg_arch_info) / sizeof(xscale_reg_t);
@@ -2833,7 +2833,7 @@ static void xscale_build_reg_cache(target_t *target)
 	if (xscale_reg_arch_type == -1)
 		xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
 
-	(*cache_p)->next = malloc(sizeof(reg_cache_t));
+	(*cache_p)->next = malloc(sizeof(struct reg_cache));
 	cache_p = &(*cache_p)->next;
 
 	/* fill in values for the xscale reg cache */

src/target/xscale.h

@@ -86,7 +86,7 @@ typedef struct xscale_common_s
 	int common_magic;
 
 	/* XScale registers (CP15, DBG) */
-	reg_cache_t *reg_cache;
+	struct reg_cache *reg_cache;
 
 	/* current state of the debug handler */
 	uint32_t handler_address;