tcl/board: add configuration for the avnet ultrazed-eg starter kit

also contains target configuration for the Xilinx UltraScale+
platform

Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4467
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
riscv-compliance-dev
Matthias Welwarsky 2018-03-13 17:03:38 +01:00 committed by Matthias Welwarsky
parent f444c57bf2
commit 7274090456
2 changed files with 106 additions and 0 deletions

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#
# AVNET UltraZED EG StarterKit
# UlraScale-EG plus IO Carrier with on-board digilent smt2
#
source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
# jtag transport only
transport select jtag
# reset lines are not wired
reset_config none
# slow default clock
adapter_khz 1000
set CHIPNAME uscale
source [find target/xilinx_ultrascale.cfg]

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#
# target configuration for
# Xilinx UltraScale+
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME uscale
}
#
# DAP tap
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x5ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
#
# PS tap
#
if { [info exists PS_TAPID] } {
set _PS_TAPID $PS_TAPID
} else {
set _PS_TAPID 0x04710093
}
set jtag_configured 0
jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
jtag configure $_CHIPNAME.ps -event setup {
global _CHIPNAME
global jtag_configured
if { $jtag_configured == 0 } {
# add the DAP tap to the chain
# See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924
irscan $_CHIPNAME.ps 0x824
drscan $_CHIPNAME.ps 32 0x00000003
runtest 100
# setup event will be re-entered through jtag arp_init
# break the recursion
set jtag_configured 1
# re-initialized the jtag chain
jtag arp_init
}
}
set _TARGETNAME $_CHIPNAME.a53
set _CTINAME $_CHIPNAME.cti
set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
set _cores 4
for { set _core 0 } { $_core < $_cores } { incr _core } {
cti create $_CTINAME.$_core -chain-position $_CHIPNAME.dap -ap-num 1 \
-ctibase [lindex $CTIBASE $_core]
set _command "target create $_TARGETNAME.$_core aarch64 -chain-position $_CHIPNAME.dap \
-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
if { $_core != 0 } {
# non-boot core examination may fail
set _command "$_command -defer-examine"
set _smp_command "$_smp_command $_TARGETNAME.$_core"
} else {
# uncomment when "hawt" rtos is merged
#set _command "$_command -rtos hawt"
set _smp_command "target smp $_TARGETNAME.$_core"
}
eval $_command
}
eval $_smp_command
targets $_TARGETNAME.0
proc core_up { args } {
global _TARGETNAME
foreach { core } [set args] {
$_TARGETNAME.$core arp_examine
}
}