Revert "target: add target->type->has_mmu fn"
This patch introduced a bug preventing flash writes from working on Cortex-M3 targets like the STM32. Moreover, it's the wrong approach for handling no-MMU targets. The right way to handle no-MMU targets is to provide accessors for physical addresses, and use them everywhere; and any code which tries to work with virtual-to-physical mappings should use a identity mapping (which can be defaulted). And ... we can tell if a target has an MMU by seeing if it's got an mmu() method. No such methood means no MMU. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
parent
d70d9634bf
commit
7269ba5eb6
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@ -56,12 +56,6 @@ extern uint8_t armv7m_gdb_dummy_cpsr_value[];
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extern reg_t armv7m_gdb_dummy_cpsr_reg;
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#endif
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static int cortex_m3_has_mmu(struct target_s *target, bool *has_mmu)
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{
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*has_mmu = false;
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return ERROR_OK;
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}
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static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
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uint32_t *value, int regnum)
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{
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@ -1998,6 +1992,5 @@ target_type_t cortexm3_target =
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.register_commands = cortex_m3_register_commands,
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.target_create = cortex_m3_target_create,
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.init_target = cortex_m3_init_target,
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.has_mmu = cortex_m3_has_mmu,
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.examine = cortex_m3_examine,
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};
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@ -496,13 +496,7 @@ static int default_virt2phys(struct target_s *target, uint32_t virtual, uint32_t
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static int default_mmu(struct target_s *target, int *enabled)
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{
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LOG_ERROR("Not implemented.");
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return ERROR_FAIL;
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}
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static int default_has_mmu(struct target_s *target, bool *has_mmu)
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{
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*has_mmu = true;
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*enabled = 0;
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return ERROR_OK;
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}
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@ -773,32 +767,14 @@ int target_mcr(struct target_s *target, int cpnum, uint32_t op1, uint32_t op2, u
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static int default_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int retval;
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bool mmu;
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retval = target->type->has_mmu(target, &mmu);
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if (retval != ERROR_OK)
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return retval;
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if (mmu)
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{
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LOG_ERROR("Not implemented");
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return ERROR_FAIL;
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}
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return target_read_memory(target, address, size, count, buffer);
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LOG_ERROR("Not implemented");
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return ERROR_FAIL;
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}
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static int default_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int retval;
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bool mmu;
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retval = target->type->has_mmu(target, &mmu);
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if (retval != ERROR_OK)
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return retval;
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if (mmu)
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{
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LOG_ERROR("Not implemented");
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return ERROR_FAIL;
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}
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return target_write_memory(target, address, size, count, buffer);
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LOG_ERROR("Not implemented");
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return ERROR_FAIL;
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}
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@ -875,10 +851,6 @@ int target_init(struct command_context_s *cmd_ctx)
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{
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target->type->mmu = default_mmu;
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}
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if (target->type->has_mmu == NULL)
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{
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target->type->has_mmu = default_has_mmu;
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}
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target = target->next;
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}
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@ -199,16 +199,8 @@ struct target_type_s
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*/
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int (*write_phys_memory)(struct target_s *target, uint32_t phys_address, uint32_t size, uint32_t count, uint8_t *buffer);
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/* returns true if the mmu is enabled. Default implementation returns error. */
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int (*mmu)(struct target_s *target, int *enabled);
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/* returns true if the target has an mmu. This can only be
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determined after the target has been examined.
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Default implementation returns success and has_mmu==true.
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*/
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int (*has_mmu)(struct target_s *target, bool *has_mmu);
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/* Read coprocessor - arm specific. Default implementation returns error. */
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int (*mrc)(struct target_s *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
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