From 70fee9207b5fd1c6f499b790591446adc4d4467c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 19 Jul 2010 08:45:45 +0200 Subject: [PATCH] arm: add error propagation to generic get_ttb fn MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- src/target/arm720t.c | 16 ++++++++++++---- src/target/arm920t.c | 5 +++-- src/target/arm920t.h | 2 +- src/target/arm926ejs.c | 6 ++++-- src/target/armv4_5_mmu.c | 5 ++++- src/target/armv4_5_mmu.h | 2 +- src/target/cortex_a8.c | 17 +++++++++++++---- src/target/xscale.c | 11 ++++++++--- 8 files changed, 46 insertions(+), 18 deletions(-) diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 0ea6cb2b0..b269f9488 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -134,16 +134,24 @@ static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t v return ERROR_OK; } -static uint32_t arm720t_get_ttb(struct target *target) +static int arm720t_get_ttb(struct target *target, uint32_t *result) { uint32_t ttb = 0x0; - arm720t_read_cp15(target, 0xee120f10, &ttb); - jtag_execute_queue(); + int retval; + + retval = arm720t_read_cp15(target, 0xee120f10, &ttb); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; ttb &= 0xffffc000; - return ttb; + *result = ttb; + + return ERROR_OK; } static void arm720t_disable_mmu_caches(struct target *target, diff --git a/src/target/arm920t.c b/src/target/arm920t.c index fe9bba7e9..9c11d124f 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -318,7 +318,7 @@ int arm920t_write_cp15_interpreted(struct target *target, } // EXPORTED to FA256 -uint32_t arm920t_get_ttb(struct target *target) +int arm920t_get_ttb(struct target *target, uint32_t *result) { int retval; uint32_t ttb = 0x0; @@ -328,7 +328,8 @@ uint32_t arm920t_get_ttb(struct target *target) 0xeebf0f51, 0x0, &ttb)) != ERROR_OK) return retval; - return ttb; + *result = ttb; + return ERROR_OK; } // EXPORTED to FA256 diff --git a/src/target/arm920t.h b/src/target/arm920t.h index a75f01ab1..9d5afab8f 100644 --- a/src/target/arm920t.h +++ b/src/target/arm920t.h @@ -66,7 +66,7 @@ int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); void arm920t_post_debug_entry(struct target *target); void arm920t_pre_restore_context(struct target *target); - uint32_t arm920t_get_ttb(struct target *target); +int arm920t_get_ttb(struct target *target, uint32_t *result); void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache); void arm920t_enable_mmu_caches(struct target *target, diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index d68e5ca34..0cf717356 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -323,7 +323,7 @@ static int arm926ejs_examine_debug_reason(struct target *target) return ERROR_OK; } -static uint32_t arm926ejs_get_ttb(struct target *target) +static int arm926ejs_get_ttb(struct target *target, uint32_t *result) { struct arm926ejs_common *arm926ejs = target_to_arm926(target); int retval; @@ -332,7 +332,9 @@ static uint32_t arm926ejs_get_ttb(struct target *target) if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK) return retval; - return ttb; + *result = ttb; + + return ERROR_OK; } static void arm926ejs_disable_mmu_caches(struct target *target, int mmu, diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c index 861410dd8..3d450ae13 100644 --- a/src/target/armv4_5_mmu.c +++ b/src/target/armv4_5_mmu.c @@ -30,8 +30,11 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a { uint32_t first_lvl_descriptor = 0x0; uint32_t second_lvl_descriptor = 0x0; - uint32_t ttb = armv4_5_mmu->get_ttb(target); + uint32_t ttb; int retval; + retval = armv4_5_mmu->get_ttb(target, &ttb); + if (retval != ERROR_OK) + return retval; retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18), diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h index 24f399342..d2716fb0f 100644 --- a/src/target/armv4_5_mmu.h +++ b/src/target/armv4_5_mmu.h @@ -26,7 +26,7 @@ struct target; struct armv4_5_mmu_common { - uint32_t (*get_ttb)(struct target *target); + int (*get_ttb)(struct target *target, uint32_t *result); int (*read_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); void (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache); diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index bd1401616..e1acbf74c 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -62,7 +62,7 @@ static void cortex_a8_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache); static void cortex_a8_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache); -static uint32_t cortex_a8_get_ttb(struct target *target); +static int cortex_a8_get_ttb(struct target *target, uint32_t *result); /* @@ -1853,8 +1853,7 @@ static int cortex_a8_target_create(struct target *target, Jim_Interp *interp) return cortex_a8_init_arch_info(target, cortex_a8, target->tap); } -/* FIX! error propagation missing from this fn */ -static uint32_t cortex_a8_get_ttb(struct target *target) +static int cortex_a8_get_ttb(struct target *target, uint32_t *result) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; @@ -1869,6 +1868,8 @@ static uint32_t cortex_a8_get_ttb(struct target *target) 0, 1, /* op1, op2 */ 2, 0, /* CRn, CRm */ &ttb); + if (retval != ERROR_OK) + return retval; } else if(cortex_a8->current_address_mode == ARM_MODE_USR) { @@ -1877,6 +1878,8 @@ static uint32_t cortex_a8_get_ttb(struct target *target) 0, 0, /* op1, op2 */ 2, 0, /* CRn, CRm */ &ttb); + if (retval != ERROR_OK) + return retval; } /* we don't know whose address is: user or kernel we assume that if we are in kernel mode then @@ -1889,6 +1892,8 @@ static uint32_t cortex_a8_get_ttb(struct target *target) 0, 1, /* op1, op2 */ 2, 0, /* CRn, CRm */ &ttb); + if (retval != ERROR_OK) + return retval; } else if(armv7a->armv4_5_common.core_mode == ARM_MODE_USR) { @@ -1897,6 +1902,8 @@ static uint32_t cortex_a8_get_ttb(struct target *target) 0, 0, /* op1, op2 */ 2, 0, /* CRn, CRm */ &ttb); + if (retval != ERROR_OK) + return retval; } /* finally we don't know whose ttb to use: user or kernel */ else @@ -1904,7 +1911,9 @@ static uint32_t cortex_a8_get_ttb(struct target *target) ttb &= 0xffffc000; - return ttb; + *result = ttb; + + return ERROR_OK; } /* FIX! error propagation missing from this fn */ diff --git a/src/target/xscale.c b/src/target/xscale.c index d5c212999..35efa8579 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -2002,15 +2002,20 @@ static int xscale_bulk_write_memory(struct target *target, uint32_t address, return xscale_write_memory(target, address, 4, count, buffer); } -static uint32_t xscale_get_ttb(struct target *target) +static int xscale_get_ttb(struct target *target, uint32_t *result) { struct xscale_common *xscale = target_to_xscale(target); uint32_t ttb; + int retval; - xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]); + retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]); + if (retval != ERROR_OK) + return retval; ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32); - return ttb; + *result = ttb; + + return ERROR_OK; } static void xscale_disable_mmu_caches(struct target *target, int mmu,