ARM11: use shared DSCR bit names
For the bits now defined in "arm_dpm.h", switch to the shared DSCR_* symbol and remove the ARM11_DSCR_* version. Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_* sibling symbol. (Note: for both ARM11 and Cortex-A8, this should arguably be enabled by default when single stepping.) Remove some other unused declarations in "arm11.h". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
eb6c880ddc
commit
6eee0729d7
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@ -40,6 +40,10 @@
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#define _DEBUG_INSTRUCTION_EXECUTION_
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#endif
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/* FIXME none of these flags should be global to all ARM11 cores!
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* Most of them shouldn't exist at all, once the code works...
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*/
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static bool arm11_config_memwrite_burst = true;
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static bool arm11_config_memwrite_error_fatal = true;
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static uint32_t arm11_vcr = 0;
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@ -59,18 +63,18 @@ static int arm11_check_init(struct arm11_common *arm11)
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CHECK_RETVAL(arm11_read_DSCR(arm11));
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LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
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if (!(arm11->dscr & ARM11_DSCR_MODE_SELECT))
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if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
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{
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LOG_DEBUG("Bringing target into debug mode");
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arm11->dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
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arm11->dscr |= DSCR_HALT_DBG_MODE;
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arm11_write_DSCR(arm11, arm11->dscr);
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/* add further reset initialization here */
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arm11->simulate_reset_on_next_halt = true;
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if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
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if (arm11->dscr & DSCR_CORE_HALTED)
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{
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/** \todo TODO: this needs further scrutiny because
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* arm11_debug_entry() never gets called. (WHY NOT?)
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@ -113,7 +117,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
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/* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
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/* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
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arm11->is_wdtr_saved = !!(arm11->dscr & ARM11_DSCR_WDTR_FULL);
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arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
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if (arm11->is_wdtr_saved)
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{
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arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
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@ -131,15 +135,13 @@ static int arm11_debug_entry(struct arm11_common *arm11)
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}
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/* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
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/* DSCR: set the Execute ARM instruction enable bit.
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*
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* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
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* but not to issue ITRs. ARM1136 seems to require this to issue
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* ITR's as well...
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* but not to issue ITRs(?). The ARMv7 arch spec says it's required
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* for executing instructions via ITR.
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*/
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arm11_write_DSCR(arm11, ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
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| arm11->dscr);
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arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
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/* From the spec:
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@ -188,7 +190,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
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return retval;
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/* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
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arm11->is_rdtr_saved = !!(arm11->dscr & ARM11_DSCR_RDTR_FULL);
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arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
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if (arm11->is_rdtr_saved)
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{
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/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
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@ -248,7 +250,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
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{
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CHECK_RETVAL(arm11_read_DSCR(arm11));
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if (arm11->dscr & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
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if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
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{
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/*
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The wDTR/rDTR two registers that are used to send/receive data to/from
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@ -324,7 +326,7 @@ static int arm11_poll(struct target *target)
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CHECK_RETVAL(arm11_check_init(arm11));
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if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
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if (arm11->dscr & DSCR_CORE_HALTED)
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{
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if (target->state != TARGET_HALTED)
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{
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@ -401,7 +403,7 @@ static int arm11_halt(struct target *target)
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{
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CHECK_RETVAL(arm11_read_DSCR(arm11));
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if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
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if (arm11->dscr & DSCR_CORE_HALTED)
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break;
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@ -529,7 +531,7 @@ static int arm11_resume(struct target *target, int current,
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LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
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if (arm11->dscr & ARM11_DSCR_CORE_RESTARTED)
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if (arm11->dscr & DSCR_CORE_RESTARTED)
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break;
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@ -674,9 +676,9 @@ static int arm11_step(struct target *target, int current,
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if (arm11_config_step_irq_enable)
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/* this disable should be redundant ... */
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arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
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arm11->dscr &= ~DSCR_INT_DIS;
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else
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arm11->dscr |= ARM11_DSCR_INTERRUPTS_DISABLE;
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arm11->dscr |= DSCR_INT_DIS;
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CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
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@ -690,8 +692,8 @@ static int arm11_step(struct target *target, int current,
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while (1)
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{
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const uint32_t mask = ARM11_DSCR_CORE_RESTARTED
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| ARM11_DSCR_CORE_HALTED;
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const uint32_t mask = DSCR_CORE_RESTARTED
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| DSCR_CORE_HALTED;
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CHECK_RETVAL(arm11_read_DSCR(arm11));
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LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
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@ -722,7 +724,7 @@ static int arm11_step(struct target *target, int current,
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CHECK_RETVAL(arm11_debug_entry(arm11));
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/* restore default state */
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arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
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arm11->dscr &= ~DSCR_INT_DIS;
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}
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@ -38,6 +38,7 @@
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} \
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} while (0)
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/* bits from ARMv7 DIDR */
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enum arm11_debug_version
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{
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ARM11_DEBUG_V6 = 0x01,
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@ -95,8 +96,6 @@ enum arm11_instructions
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enum arm11_dscr
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{
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ARM11_DSCR_CORE_HALTED = 1 << 0,
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ARM11_DSCR_CORE_RESTARTED = 1 << 1,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
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@ -105,20 +104,6 @@ enum arm11_dscr
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
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ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
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ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
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ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
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ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
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ARM11_DSCR_MODE_SELECT = 1 << 14,
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ARM11_DSCR_WDTR_FULL = 1 << 29,
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ARM11_DSCR_RDTR_FULL = 1 << 30,
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};
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enum arm11_cpsr
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{
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ARM11_CPSR_T = 1 << 5,
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ARM11_CPSR_J = 1 << 24,
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};
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enum arm11_sc7
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@ -132,10 +117,4 @@ enum arm11_sc7
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ARM11_SC7_WCR0 = 112,
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};
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struct arm11_reg_state
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{
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uint32_t def_index;
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struct target * target;
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};
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#endif /* ARM11_H */
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@ -141,6 +141,7 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
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*/
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#define DSCR_CORE_HALTED (1 << 0)
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#define DSCR_CORE_RESTARTED (1 << 1)
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#define DSCR_INT_DIS (1 << 11)
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#define DSCR_ITR_EN (1 << 13)
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#define DSCR_HALT_DBG_MODE (1 << 14)
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#define DSCR_MON_DBG_MODE (1 << 15)
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