ARM11 command handling fixes
- Commands were supposed to have been "arm11 memwrite ..." not "memwrite ..." - Get rid of obfuscatory macros - Re-alphabetize - Add docs for "arm11 vcr" git-svn-id: svn://svn.berlios.de/openocd/trunk@2776 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
dbrownell
parent
4297209ac9
commit
6d4cdddbe2
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@ -5496,10 +5496,23 @@ If @var{value} is defined, first assigns that.
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@deffn Command {arm11 step_irq_enable} [value]
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Displays the value of the flag controlling whether
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IRQs are enabled during single stepping;
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they is disabled by default.
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they are disabled by default.
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If @var{value} is defined, first assigns that.
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@end deffn
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@deffn Command {arm11 vcr} [value]
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@cindex vector_catch
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Displays the value of the @emph{Vector Catch Register (VCR)},
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coprocessor 14 register 7.
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If @var{value} is defined, first assigns that.
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Vector Catch hardware provides dedicated breakpoints
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for certain hardware events.
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The specific bit values are core-specific (as in fact is using
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coprocessor 14 register 7 itself) but all current ARM11
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cores @emph{except the ARM1176} use the same six bits.
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@end deffn
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@section ARMv7 Architecture
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@cindex ARMv7
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@ -1905,19 +1905,6 @@ int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char
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return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
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}
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#define RC_TOP(name, descr, more) \
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{ \
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command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
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command_t * top_cmd = new_cmd; \
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more \
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}
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#define RC_FINAL(name, descr, handler) \
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register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
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#define RC_FINAL_BOOL(name, descr, var) \
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register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
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BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
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BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
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BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
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@ -2069,36 +2056,49 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
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{
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FNC_INFO;
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command_t * top_cmd = NULL;
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command_t *top_cmd, *mw_cmd;
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RC_TOP("arm11", "arm11 specific commands",
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top_cmd = register_command(cmd_ctx, NULL, "arm11",
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NULL, COMMAND_ANY, NULL);
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RC_TOP("memwrite", "Control memory write transfer mode",
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/* "hardware_step" is only here to check if the default
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* simulate + breakpoint implementation is broken.
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* TEMPORARY! NOT DOCUMENTED!
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*/
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register_command(cmd_ctx, top_cmd, "hardware_step",
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arm11_handle_bool_hardware_step, COMMAND_ANY,
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"DEBUG ONLY - Hardware single stepping"
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" (default: disabled)");
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RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
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memwrite_burst)
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register_command(cmd_ctx, top_cmd, "mcr",
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arm11_handle_mcr, COMMAND_ANY,
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"Write Coprocessor register");
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RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
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memwrite_error_fatal)
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) /* memwrite */
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mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
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NULL, COMMAND_ANY, NULL);
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register_command(cmd_ctx, mw_cmd, "burst",
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arm11_handle_bool_memwrite_burst, COMMAND_ANY,
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"Enable/Disable non-standard but fast burst mode"
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" (default: enabled)");
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register_command(cmd_ctx, mw_cmd, "error_fatal",
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arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
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"Terminate program if transfer error was found"
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" (default: enabled)");
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RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
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memrw_no_increment)
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RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
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step_irq_enable)
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RC_FINAL_BOOL("hardware_step", "hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.",
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hardware_step)
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RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
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arm11_handle_vcr)
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RC_FINAL("mrc", "Read Coprocessor register",
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arm11_handle_mrc)
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RC_FINAL("mcr", "Write Coprocessor register",
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arm11_handle_mcr)
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) /* arm11 */
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register_command(cmd_ctx, top_cmd, "mrc",
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arm11_handle_mrc, COMMAND_ANY,
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"Read Coprocessor register");
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register_command(cmd_ctx, top_cmd, "no_increment",
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arm11_handle_bool_memrw_no_increment, COMMAND_ANY,
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"Don't increment address on multi-read/-write"
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" (default: disabled)");
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register_command(cmd_ctx, top_cmd, "step_irq_enable",
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arm11_handle_bool_step_irq_enable, COMMAND_ANY,
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"Enable interrupts while stepping"
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" (default: disabled)");
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register_command(cmd_ctx, top_cmd, "vcr",
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arm11_handle_vcr, COMMAND_ANY,
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"Control (Interrupt) Vector Catch Register");
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return ERROR_OK;
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}
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