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- check cortex_m3 FPB is enabled when setting hardware breakpoint 

- Thanks Igor Skochinsky

git-svn-id: svn://svn.berlios.de/openocd/trunk@1231 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
ntfreak 2008-12-12 22:14:21 +00:00
parent d44c70a4b0
commit 6c27550f6e
2 changed files with 11 additions and 3 deletions
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9
src/target/cortex_m3.c
View File

@ -225,6 +225,7 @@ int cortex_m3_endreset_event(target_t *target)
/* Enable FPB */ /* Enable FPB */
target_write_u32(target, FP_CTRL, 3); target_write_u32(target, FP_CTRL, 3);
cortex_m3->fpb_enabled = 1;
/* Restore FPB registers */ /* Restore FPB registers */
for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
@ -869,6 +870,11 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1; comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value); target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
LOG_DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value); LOG_DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value);
if (!cortex_m3->fpb_enabled)
{
LOG_DEBUG("FPB wasn't enabled, do it now");
target_write_u32(target, FP_CTRL, 3);
}
} }
else if (breakpoint->type == BKPT_SOFT) else if (breakpoint->type == BKPT_SOFT)
{ {
@ -1401,10 +1407,11 @@ int cortex_m3_examine(struct target_s *target)
/* Setup FPB */ /* Setup FPB */
target_read_u32(target, FP_CTRL, &fpcr); target_read_u32(target, FP_CTRL, &fpcr);
cortex_m3->auto_bp_type = 1; cortex_m3->auto_bp_type = 1;
cortex_m3->fp_num_code = (fpcr >> 4) & 0xF; cortex_m3->fp_num_code = (fpcr >> 8) & 0x70 | (fpcr >> 4) & 0xF; /* bits [14:12] and [7:4] */
cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
cortex_m3->fp_code_available = cortex_m3->fp_num_code; cortex_m3->fp_code_available = cortex_m3->fp_num_code;
cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t));
cortex_m3->fpb_enabled = fpcr & 1;
for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
{ {
cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;

5
src/target/cortex_m3.h
View File

@ -145,14 +145,15 @@ typedef struct cortex_m3_common_s
u32 nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */ u32 nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
u32 nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */ u32 nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
/* Flash Patch and Breakpoint */ /* Flash Patch and Breakpoint (FPB) */
int fp_num_lit; int fp_num_lit;
int fp_num_code; int fp_num_code;
int fp_code_available; int fp_code_available;
int fpb_enabled;
int auto_bp_type; int auto_bp_type;
cortex_m3_fp_comparator_t *fp_comparator_list; cortex_m3_fp_comparator_t *fp_comparator_list;
/* DWT */ /* Data Watchpoint and Trace (DWT) */
int dwt_num_comp; int dwt_num_comp;
int dwt_comp_available; int dwt_comp_available;
cortex_m3_dwt_comparator_t *dwt_comparator_list; cortex_m3_dwt_comparator_t *dwt_comparator_list;