zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

David Brownell <david-b@pacbell.net> Mention how parallel clock voting implementations of RTCK work, 

and reference TI's free VHDL code.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2508 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
oharboe 2009-07-12 14:08:16 +00:00
parent 5627e841e3
commit 6996e628f8
1 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
doc/openocd.texi
View File

@ -5661,6 +5661,18 @@ held device example'' - the adaptiveness works perfectly all the
time. One can set a break point or halt the system in the deep power time. One can set a break point or halt the system in the deep power
down code, slow step out until the system speeds up. down code, slow step out until the system speeds up.
Note that adaptive clocking may also need to work at the board level,
when a board-level scan chain has multiple chips.
Parallel clock voting schemes are good way to implement this,
both within and between chips, and can easily be implemented
with a CPLD.
It's not difficult to have logic fan a module's input TCK signal out
to each TAP in the scan chain, and then wait until each TAP's RTCK comes
back with the right polarity before changing the output RTCK signal.
Texas Instruments makes some clock voting logic available
for free (with no support) in VHDL form; see
@url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
@b{Solution #2 - Always works - but may be slower} @b{Solution #2 - Always works - but may be slower}
Often this is a perfectly acceptable solution. Often this is a perfectly acceptable solution.