- add support for cortex_m3 target_request debugmsgs
- target request handler disabled by default until a target has been registered git-svn-id: svn://svn.berlios.de/openocd/trunk@259 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
ntfreak
parent
1796e1602e
commit
68b97e4b5c
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@ -638,6 +638,9 @@ int arm7_9_handle_target_request(void *priv)
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
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if (!target->dbg_msg_enabled)
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return ERROR_OK;
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if (target->state == TARGET_RUNNING)
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{
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/* read DCC control register */
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@ -30,6 +30,7 @@
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#include "register.h"
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#include "target.h"
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#include "target_request.h"
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#include "log.h"
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#include "jtag.h"
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#include "arm_jtag.h"
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@ -50,7 +51,8 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
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int cortex_m3_quit();
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int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value);
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int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value);
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int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer);
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target_type_t cortexm3_target =
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{
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.name = "cortex_m3",
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@ -58,8 +60,8 @@ target_type_t cortexm3_target =
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.poll = cortex_m3_poll,
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.arch_state = armv7m_arch_state,
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.target_request_data = NULL,
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.target_request_data = cortex_m3_target_request_data,
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.halt = cortex_m3_halt,
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.resume = cortex_m3_resume,
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.step = cortex_m3_step,
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@ -168,6 +170,8 @@ int cortex_m3_endreset_event(target_t *target)
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ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
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DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
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ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
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/* Enable debug requests */
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ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
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if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
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@ -216,15 +220,15 @@ int cortex_m3_examine_debug_reason(target_t *target)
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if ((target->debug_reason != DBG_REASON_DBGRQ)
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&& (target->debug_reason != DBG_REASON_SINGLESTEP))
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{
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/* INCOPMPLETE */
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/* INCOMPLETE */
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if (cortex_m3->nvic_dfsr & 0x2)
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if (cortex_m3->nvic_dfsr & DFSR_BKPT)
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{
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target->debug_reason = DBG_REASON_BREAKPOINT;
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if (cortex_m3->nvic_dfsr & 0x4)
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if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
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target->debug_reason = DBG_REASON_WPTANDBKPT;
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}
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else if (cortex_m3->nvic_dfsr & 0x4)
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else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
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target->debug_reason = DBG_REASON_WATCHPOINT;
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}
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@ -701,6 +705,8 @@ int cortex_m3_assert_reset(target_t *target)
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DEBUG("target->state: %s", target_state_strings[target->state]);
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ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
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if (target->reset_mode == RESET_RUN)
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{
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/* Set/Clear C_MASKINTS in a separate operation */
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@ -1353,6 +1359,77 @@ int cortex_m3_quit()
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return ERROR_OK;
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}
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int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
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{
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u16 dcrdr;
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ahbap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
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*ctrl = (u8)dcrdr;
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*value = (u8)(dcrdr >> 8);
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DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
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/* write ack back to software dcc register
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* signify we have read data */
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dcrdr = 0;
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ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
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return ERROR_OK;
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}
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int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer)
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{
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armv7m_common_t *armv7m = target->arch_info;
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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u8 data;
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u8 ctrl;
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int i;
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for (i = 0; i < (size * 4); i++)
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{
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cortex_m3_dcc_read(swjdp, &data, &ctrl);
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buffer[i] = data;
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}
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return ERROR_OK;
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}
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int cortex_m3_handle_target_request(void *priv)
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{
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target_t *target = priv;
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armv7m_common_t *armv7m = target->arch_info;
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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if (!target->dbg_msg_enabled)
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return ERROR_OK;
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if (target->state == TARGET_RUNNING)
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{
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u8 data;
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u8 ctrl;
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cortex_m3_dcc_read(swjdp, &data, &ctrl);
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/* check if we have data */
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if (ctrl & (1<<0))
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{
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u32 request;
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request = data;
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cortex_m3_dcc_read(swjdp, &data, &ctrl);
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request |= (data << 8);
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cortex_m3_dcc_read(swjdp, &data, &ctrl);
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request |= (data << 16);
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cortex_m3_dcc_read(swjdp, &data, &ctrl);
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request |= (data << 24);
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target_request(target, request);
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}
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}
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return ERROR_OK;
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}
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int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant)
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{
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armv7m_common_t *armv7m;
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@ -1387,6 +1464,8 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
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armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
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// armv7m->full_context = cortex_m3_full_context;
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target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
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return ERROR_OK;
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}
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@ -101,10 +101,10 @@ extern char* cortex_m3_state_strings[];
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/* NVIC_SHCSR bits */
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#define SHCSR_BUSFAULTENA (1<<17)
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/* NVIC_DFSR bits */
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#define DFSR_HALTED 1
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#define DFSR_BKPT 2
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#define DFSR_DWTTRAP 4
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#define DFSR_VCATCH 8
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#define DFSR_HALTED 1
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#define DFSR_BKPT 2
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#define DFSR_DWTTRAP 4
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#define DFSR_VCATCH 8
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#define FPCR_CODE 0
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#define FPCR_LITERAL 1
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@ -613,6 +613,11 @@ int ahbap_block_read_u32(swjdp_common_t *swjdp, u32 *buffer, int count, u32 addr
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int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
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{
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int retval;
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u32 dcrdr;
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ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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/* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
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@ -623,11 +628,18 @@ int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
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ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
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ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
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return swjdp_transaction_endcheck(swjdp);
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retval = swjdp_transaction_endcheck(swjdp);
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ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
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return retval;
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}
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int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
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{
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int retval;
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u32 dcrdr;
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ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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/* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
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@ -637,8 +649,10 @@ int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
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/* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
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ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
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ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
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return swjdp_transaction_endcheck(swjdp);
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retval = swjdp_transaction_endcheck(swjdp);
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ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
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return retval;
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}
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int ahbap_debugport_init(swjdp_common_t *swjdp)
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@ -1065,7 +1065,8 @@ int handle_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a
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(*last_target_p)->trace_info->trace_history_overflowed = 0;
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(*last_target_p)->dbgmsg = NULL;
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(*last_target_p)->dbg_msg_enabled = 0;
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(*last_target_p)->type->target_command(cmd_ctx, cmd, args, argc, *last_target_p);
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found = 1;
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@ -170,6 +170,7 @@ typedef struct target_s
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struct watchpoint_s *watchpoints; /* list of watchpoints */
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struct trace_s *trace_info; /* generic trace information */
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struct debug_msg_receiver_s *dbgmsg;/* list of debug message receivers */
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u32 dbg_msg_enabled; /* debug message status */
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void *arch_info; /* architecture specific information */
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struct target_s *next; /* next target in list */
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} target_t;
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@ -83,6 +83,8 @@ int target_hexmsg(target_t *target, int size, u32 length)
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if ((i%8 == 7) || (i == length - 1))
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{
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DEBUG("%s", line);
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while (c)
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{
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command_print(c->cmd_ctx, "%s", line);
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@ -153,6 +155,9 @@ int add_debug_msg_receiver(struct command_context_s *cmd_ctx, target_t *target)
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(*p)->cmd_ctx = cmd_ctx;
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(*p)->next = NULL;
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/* enable callback */
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target->dbg_msg_enabled = 1;
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return ERROR_OK;
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}
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@ -217,6 +222,11 @@ int delete_debug_msg_receiver(struct command_context_s *cmd_ctx, target_t *targe
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{
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*p = next;
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free(c);
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if (*p == NULL)
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{
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/* disable callback */
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target->dbg_msg_enabled = 0;
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}
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return ERROR_OK;
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}
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else
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