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From Michael Bruck 

- bugfix in server.c
- removed unused parameter from jtag_add_ir_scan et al. This
wasn't necessary in hindsight but anyway.
- arm11 source committed but not not in Makefile.am/target.c for now.

git-svn-id: svn://svn.berlios.de/openocd/trunk@341 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
oharboe 2008-02-25 08:22:18 +00:00
parent 4edcbe0a54
commit 687a9553c9
21 changed files with 21600 additions and 19380 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/flash/str9xpec.c
View File

@ -148,7 +148,7 @@ int str9xpec_set_instr(int chain_pos, u32 new_instr, enum tap_state end_state)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, end_state, NULL);
jtag_add_ir_scan(1, &field, end_state);
free(field.out_value);
}
@ -174,7 +174,7 @@ u8 str9xpec_isc_status(int chain_pos)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
DEBUG("status: 0x%2.2x", status);
@ -266,7 +266,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
status = str9xpec_isc_status(chain_pos);
@ -409,7 +409,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_sleep(40000);
/* read blank check result */
@ -423,7 +423,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_PI, NULL);
jtag_add_dr_scan(1, &field, TAP_PI);
jtag_execute_queue();
status = str9xpec_isc_status(chain_pos);
@ -525,7 +525,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
jtag_add_sleep(10);
@ -591,7 +591,7 @@ int str9xpec_lock_device(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
jtag_execute_queue();
} while(!(status & ISC_STATUS_BUSY));
@ -677,7 +677,7 @@ int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
return ERROR_OK;
}
@ -766,7 +766,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
/* small delay before polling */
jtag_add_sleep(50);
@ -784,7 +784,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
jtag_execute_queue();
status = buf_get_u32(scanbuf, 0, 8);
@ -826,7 +826,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
/* small delay before polling */
jtag_add_sleep(50);
@ -844,7 +844,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
jtag_execute_queue();
status = buf_get_u32(scanbuf, 0, 8);
@ -908,7 +908,7 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
idcode = buf_get_u32(buffer, 0, 32);
@ -1033,7 +1033,7 @@ int str9xpec_write_options(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
/* small delay before polling */
jtag_add_sleep(50);
@ -1051,7 +1051,7 @@ int str9xpec_write_options(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
jtag_execute_queue();
} while(!(status & ISC_STATUS_BUSY));

17
src/jtag/jtag.c
View File

@ -379,7 +379,7 @@ void cmd_queue_free()
cmd_queue_pages = NULL;
}
int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state, void *dummy_anachronism)
int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
jtag_command_t **last_cmd;
jtag_device_t *device;
@ -472,7 +472,7 @@ int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state,
return ERROR_OK;
}
int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state, void *dummy_anachronism)
int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
jtag_command_t **last_cmd;
int i;
@ -526,7 +526,7 @@ int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state
return ERROR_OK;
}
int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state, void *dummy_anachronism)
int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
int i, j;
int bypass_devices = 0;
@ -625,7 +625,8 @@ int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state,
return ERROR_OK;
}
int jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state, void *dummy_anachronism)
int jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
int i;
jtag_command_t **last_cmd = jtag_get_last_command_p();
@ -1168,7 +1169,7 @@ int jtag_examine_chain()
buf_set_u32(idcode_buffer, i * 32, 32, 0x000000FF);
}
jtag_add_plain_dr_scan(1, &field, TAP_TLR, NULL);
jtag_add_plain_dr_scan(1, &field, TAP_TLR);
jtag_execute_queue();
for (i = 0; i < JTAG_MAX_CHAIN_SIZE * 4; i++)
@ -1264,7 +1265,7 @@ int jtag_validate_chain()
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_plain_ir_scan(1, &field, TAP_TLR, NULL);
jtag_add_plain_ir_scan(1, &field, TAP_TLR);
jtag_execute_queue();
device = jtag_devices;
@ -1740,7 +1741,7 @@ int handle_irscan_command(struct command_context_s *cmd_ctx, char *cmd, char **a
fields[i].in_handler_priv = NULL;
}
jtag_add_ir_scan(argc / 2, fields, -1, NULL);
jtag_add_ir_scan(argc / 2, fields, -1);
jtag_execute_queue();
for (i = 0; i < argc / 2; i++)
@ -1799,7 +1800,7 @@ int handle_drscan_command(struct command_context_s *cmd_ctx, char *cmd, char **a
}
}
jtag_add_dr_scan(num_fields, fields, -1, NULL);
jtag_add_dr_scan(num_fields, fields, -1);
jtag_execute_queue();
for (i = 0; i < argc / 2; i++)

8
src/jtag/jtag.h
View File

@ -244,10 +244,10 @@ extern int jtag_init(struct command_context_s *cmd_ctx);
extern int jtag_register_commands(struct command_context_s *cmd_ctx);
/* JTAG interface, can be implemented with a software or hardware fifo */
extern int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate, void *dummy_anachronism);
extern int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate, void *dummy_anachronism);
extern int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate, void *dummy_anachronism);
extern int jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate, void *dummy_anachronism);
extern int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern int jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
/* execute a state transition within the JTAG standard, but the exact path
* path that is taken is undefined. Many implementations use precisely
* 7 clocks to perform a transition, but it could be more or less

8
src/pld/virtex2.c
View File

@ -62,7 +62,7 @@ int virtex2_set_instr(int chain_pos, u32 new_instr)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, TAP_RTI, NULL);
jtag_add_ir_scan(1, &field, TAP_RTI);
free(field.out_value);
}
@ -94,7 +94,7 @@ int virtex2_send_32(struct pld_device_s *pld_device, int num_words, u32 *words)
virtex2_set_instr(virtex2_info->chain_pos, 0x5); /* CFG_IN */
jtag_add_dr_scan(1, &scan_field, TAP_PD, NULL);
jtag_add_dr_scan(1, &scan_field, TAP_PD);
free(values);
@ -127,7 +127,7 @@ int virtex2_receive_32(struct pld_device_s *pld_device, int num_words, u32 *word
while (num_words--)
{
scan_field.in_handler_priv = words++;
jtag_add_dr_scan(1, &scan_field, TAP_PD, NULL);
jtag_add_dr_scan(1, &scan_field, TAP_PD);
}
return ERROR_OK;
@ -189,7 +189,7 @@ int virtex2_load(struct pld_device_s *pld_device, char *filename)
field.num_bits = bit_file.length * 8;
field.out_value = bit_file.data;
jtag_add_dr_scan(1, &field, TAP_PD, NULL);
jtag_add_dr_scan(1, &field, TAP_PD);
jtag_execute_queue();
jtag_add_statemove(TAP_TLR);

1358
src/target/arm11.c Normal file
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File diff suppressed because it is too large Load Diff

250
src/target/arm11.h Normal file
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@ -0,0 +1,250 @@
/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef ARM11_H
#define ARM11_H
#include "target.h"
#include "register.h"
#include "embeddedice.h"
#include "arm_jtag.h"
#define bool int
#define true 1
#define false 0
#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
#define NEW(type, variable, items) \
type * variable = malloc(sizeof(type) * items)
#define ARM11_REGCACHE_MODEREGS 0
#define ARM11_REGCACHE_FREGS 0
#define ARM11_REGCACHE_COUNT (20 + \
23 * ARM11_REGCACHE_MODEREGS + \
9 * ARM11_REGCACHE_FREGS)
typedef struct arm11_register_history_s
{
u32 value;
u8 valid;
}arm11_register_history_t;
typedef struct arm11_common_s
{
target_t * target;
arm_jtag_t jtag_info;
/** \name Processor type detection */
/*@{*/
u32 device_id; /**< IDCODE readout */
u32 didr; /**< DIDR readout (debug capabilities) */
u8 implementor; /**< DIDR Implementor readout */
size_t brp; /**< Number of Breakpoint Register Pairs */
size_t wrp; /**< Number of Watchpoint Register Pairs */
/*@}*/
u32 last_dscr; /**< Last retrieved DSCR value;
* Can be used to detect changes */
u8 trst_active;
u8 halt_requested;
/** \name Shadow registers to save processor state */
/*@{*/
reg_t * reg_list; /**< target register list */
u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/
arm11_register_history_t
reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
} arm11_common_t;
/**
* ARM11 DBGTAP instructions
*
* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
*/
enum arm11_instructions
{
ARM11_EXTEST = 0x00,
ARM11_SCAN_N = 0x02,
ARM11_RESTART = 0x04,
ARM11_HALT = 0x08,
ARM11_INTEST = 0x0C,
ARM11_ITRSEL = 0x1D,
ARM11_IDCODE = 0x1E,
ARM11_BYPASS = 0x1F,
};
enum arm11_dscr
{
ARM11_DSCR_CORE_HALTED = 1 << 0,
ARM11_DSCR_CORE_RESTARTED = 1 << 1,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
ARM11_DSCR_MODE_SELECT = 1 << 14,
ARM11_DSCR_WDTR_FULL = 1 << 29,
ARM11_DSCR_RDTR_FULL = 1 << 30,
};
enum arm11_cpsr
{
ARM11_CPSR_T = 1 << 5,
ARM11_CPSR_J = 1 << 24,
};
enum arm11_sc7
{
ARM11_SC7_NULL = 0,
ARM11_SC7_VCR = 7,
ARM11_SC7_PC = 8,
ARM11_SC7_BVR0 = 64,
ARM11_SC7_BCR0 = 80,
ARM11_SC7_WVR0 = 96,
ARM11_SC7_WCR0 = 112,
};
typedef struct arm11_reg_state_s
{
u32 def_index;
target_t * target;
} arm11_reg_state_t;
/* poll current target status */
int arm11_poll(struct target_s *target);
/* architecture specific status reply */
int arm11_arch_state(struct target_s *target);
/* target request support */
int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
/* target execution control */
int arm11_halt(struct target_s *target);
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
/* target reset control */
int arm11_assert_reset(struct target_s *target);
int arm11_deassert_reset(struct target_s *target);
int arm11_soft_reset_halt(struct target_s *target);
int arm11_prepare_reset_halt(struct target_s *target);
/* target register access for gdb */
int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
/* target memory access
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
/* target break-/watchpoint control
* rw: 0 = write, 1 = read, 2 = access
*/
int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
/* target algorithm support */
int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
int arm11_register_commands(struct command_context_s *cmd_ctx);
int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm11_quit(void);
/* helpers */
void arm11_build_reg_cache(target_t *target);
/* internals */
void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
void arm11_add_IR (arm11_common_t * arm11, u8 instr, enum tap_state state);
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, enum tap_state state);
void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state);
u32 arm11_read_DSCR (arm11_common_t * arm11);
void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
void arm11_run_instr_data_prepare (arm11_common_t * arm11);
void arm11_run_instr_data_finish (arm11_common_t * arm11);
void arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
void arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
void arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
void arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
typedef struct arm11_sc7_action_s
{
bool write;
u8 address;
u32 value;
} arm11_sc7_action_t;
void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
void arm11_sc7_clear_bw(arm11_common_t * arm11);
#endif /* ARM11_H */

611
src/target/arm11_dbgtap.c Normal file
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@ -0,0 +1,611 @@
/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "arm11.h"
#include "jtag.h"
#include "log.h"
#include <stdlib.h>
#include <string.h>
#if 0
#define JTAG_DEBUG(expr ...) \
do { \
log_printf (LOG_DEBUG, __FILE__, __LINE__, __FUNCTION__, expr); \
} while(0)
#else
#define JTAG_DEBUG(expr ...) \
do {} while(0)
#endif
/** Code de-clutter: Construct scan_field_t to write out a value
*
* \param arm11 Target state variable.
* \param num_bits Length of the data field
* \param out_data pointer to the data that will be sent out
* <em>(data is read when it is added to the JTAG queue)</em>
* \param in_data pointer to the memory that will receive data that was clocked in
* <em>(data is written when the JTAG queue is executed)</em>
* \param field target data structure that will be initialized
*/
void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
{
field->device = arm11->jtag_info.chain_pos;
field->num_bits = num_bits;
field->out_mask = NULL;
field->in_check_mask = NULL;
field->in_check_value = NULL;
field->in_handler = NULL;
field->in_handler_priv = NULL;
field->out_value = out_data;
field->in_value = in_data;
}
/** Write JTAG instruction register
*
* \param arm11 Target state variable.
* \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
* \param state Pass the final TAP state or -1 for the default value (Pause-IR).
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state)
{
jtag_device_t *device = jtag_get_device(arm11->jtag_info.chain_pos);
if (buf_get_u32(device->cur_instr, 0, 5) == instr)
{
JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
return;
}
JTAG_DEBUG("IR <= 0x%02x", instr);
scan_field_t field;
arm11_setup_field(arm11, 5, &instr, NULL, &field);
jtag_add_ir_scan_vc(1, &field, state == -1 ? TAP_PI : state);
}
/** Verify shifted out data from Scan Chain Register (SCREG)
* Used as parameter to scan_field_t::in_handler in
* arm11_add_debug_SCAN_N().
*
*/
static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field)
{
/** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
u8 v = *in_value & 0x1F;
if (v != 0x10)
{
ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
exit(-1);
}
JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
return ERROR_OK;
}
/** Select and write to Scan Chain Register (SCREG)
*
* This function sets the instruction register to SCAN_N and writes
* the data register with the selected chain number.
*
* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
*
* \param arm11 Target state variable.
* \param chain Scan chain that will be selected.
* \param state Pass the final TAP state or -1 for the default
* value (Pause-DR).
*
* The chain takes effect when Update-DR is passed (usually when subsequently
* the INTEXT/EXTEST instructions are written).
*
* \warning (Obsolete) Using this twice in a row will \em fail. The first call will end
* in Pause-DR. The second call, due to the IR caching, will not
* go through Capture-DR when shifting in the new scan chain number.
* As a result the verification in arm11_in_handler_SCAN_N() must
* fail.
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state state)
{
JTAG_DEBUG("SCREG <= 0x%02x", chain);
arm11_add_IR(arm11, ARM11_SCAN_N, -1);
scan_field_t field;
arm11_setup_field(arm11, 5, &chain, NULL, &field);
field.in_handler = arm11_in_handler_SCAN_N;
jtag_add_dr_scan_vc(1, &field, state == -1 ? TAP_PD : state);
}
/** Write an instruction into the ITR register
*
* \param arm11 Target state variable.
* \param inst An ARM11 processor instruction/opcode.
* \param flag Optional parameter to retrieve the InstCompl flag
* (this will be written when the JTAG chain is executed).
* \param state Pass the final TAP state or -1 for the default
* value (Run-Test/Idle).
*
* \remarks By default this ends with Run-Test/Idle state
* and causes the instruction to be executed. If
* a subsequent write to DTR is needed before
* executing the instruction then TAP_PD should be
* passed to \p state.
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state)
{
JTAG_DEBUG("INST <= 0x%08x", inst);
scan_field_t itr[2];
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
jtag_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_RTI : state);
}
/** Read the Debug Status and Control Register (DSCR)
*
* same as CP14 c1
*
* \param arm11 Target state variable.
* \return DSCR content
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
u32 arm11_read_DSCR(arm11_common_t * arm11)
{
arm11_add_debug_SCAN_N(arm11, 0x01, -1);
arm11_add_IR(arm11, ARM11_INTEST, -1);
u32 dscr;
scan_field_t chain1_field;
arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
jtag_add_dr_scan_vc(1, &chain1_field, TAP_PD);
jtag_execute_queue();
if (arm11->last_dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
return dscr;
}
/** Write the Debug Status and Control Register (DSCR)
*
* same as CP14 c1
*
* \param arm11 Target state variable.
* \param dscr DSCR content
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
{
arm11_add_debug_SCAN_N(arm11, 0x01, -1);
arm11_add_IR(arm11, ARM11_EXTEST, -1);
scan_field_t chain1_field;
arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
jtag_add_dr_scan_vc(1, &chain1_field, TAP_PD);
jtag_execute_queue();
JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
}
/** Get the debug reason from Debug Status and Control Register (DSCR)
*
* \param dscr DSCR value to analyze
* \return Debug reason
*
*/
enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
{
switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
{
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT: return DBG_REASON_DBGRQ;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT: return DBG_REASON_BREAKPOINT;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT: return DBG_REASON_WATCHPOINT;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION: return DBG_REASON_BREAKPOINT;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ: return DBG_REASON_DBGRQ;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH: return DBG_REASON_BREAKPOINT;
default:
return DBG_REASON_DBGRQ;
}
};
/** Prepare the stage for ITR/DTR operations
* from the arm11_run_instr... group of functions.
*
* Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
* around a block of arm11_run_instr_... calls.
*
* Select scan chain 5 to allow quick access to DTR. When scan
* chain 4 is needed to put in a register the ITRSel instruction
* shortcut is used instead of actually changing the Scan_N
* register.
*
* \param arm11 Target state variable.
*
*/
void arm11_run_instr_data_prepare(arm11_common_t * arm11)
{
arm11_add_debug_SCAN_N(arm11, 0x05, -1);
}
/** Cleanup after ITR/DTR operations
* from the arm11_run_instr... group of functions
*
* Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
* around a block of arm11_run_instr_... calls.
*
* Any RTI can lead to an instruction execution when
* scan chains 4 or 5 are selected and the IR holds
* INTEST or EXTEST. So we must disable that before
* any following activities lead to an RTI.
*
* \param arm11 Target state variable.
*
*/
void arm11_run_instr_data_finish(arm11_common_t * arm11)
{
arm11_add_debug_SCAN_N(arm11, 0x00, -1);
}
/** Execute one or multiple instructions via ITR
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
*
* \param arm11 Target state variable.
* \param opcode Pointer to sequence of ARM opcodes
* \param count Number of opcodes to execute
*
*/
void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
while (count--)
{
arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_RTI);
while (1)
{
u8 flag;
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_RTI : TAP_PD);
jtag_execute_queue();
if (flag)
break;
}
}
}
/** Execute one instruction via ITR
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
*
* \param arm11 Target state variable.
* \param opcode ARM opcode
*
*/
void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
{
arm11_run_instr_no_data(arm11, &opcode, 1);
}
/** Execute one instruction via ITR repeatedly while
* passing data to the core via DTR on each execution.
*
* The executed instruction \em must read data from DTR.
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
*
* \param arm11 Target state variable.
* \param opcode ARM opcode
* \param data Pointer to the data words to be passed to the core
* \param count Number of data words and instruction repetitions
*
*/
void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD);
arm11_add_IR(arm11, ARM11_EXTEST, -1);
scan_field_t chain5_fields[3];
u32 Data;
u8 Ready;
u8 nRetry;
arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
while (count--)
{
do
{
Data = *data;
jtag_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_RTI);
jtag_execute_queue();
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
}
while (!Ready);
data++;
}
arm11_add_IR(arm11, ARM11_INTEST, -1);
do
{
Data = 0;
jtag_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
jtag_execute_queue();
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
while (!Ready);
}
/** Execute an instruction via ITR while handing data into the core via DTR.
*
* The executed instruction \em must read data from DTR.
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
*
* \param arm11 Target state variable.
* \param opcode ARM opcode
* \param data Data word to be passed to the core via DTR
*
*/
void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
{
arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
}
/** Execute one instruction via ITR repeatedly while
* reading data from the core via DTR on each execution.
*
* The executed instruction \em must write data to DTR.
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
*
* \param arm11 Target state variable.
* \param opcode ARM opcode
* \param data Pointer to an array that receives the data words from the core
* \param count Number of data words and instruction repetitions
*
*/
void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_RTI);
arm11_add_IR(arm11, ARM11_INTEST, -1);
scan_field_t chain5_fields[3];
u32 Data;
u8 Ready;
u8 nRetry;
arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
while (count--)
{
do
{
jtag_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_RTI : TAP_PD);
jtag_execute_queue();
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
while (!Ready);
*data++ = Data;
}
}
/** Execute one instruction via ITR
* then load r0 into DTR and read DTR from core.
*
* The first executed instruction (\p opcode) should write data to r0.
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
*
* \param arm11 Target state variable.
* \param opcode ARM opcode to write r0 with the value of interest
* \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
*
*/
void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
{
arm11_run_instr_no_data1(arm11, opcode);
/* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
}
/** Load data into core via DTR then move it to r0 then
* execute one instruction via ITR
*
* The final executed instruction (\p opcode) should read data from r0.
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
*
* \param arm11 Target state variable.
* \param opcode ARM opcode to read r0 act upon it
* \param data Data word that will be written to r0 before \p opcode is executed
*
*/
void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
{
/* MRC p14,0,r0,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
arm11_run_instr_no_data1(arm11, opcode);
}
void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
{
arm11_add_debug_SCAN_N(arm11, 0x07, -1);
arm11_add_IR(arm11, ARM11_EXTEST, -1);
scan_field_t chain7_fields[3];
u8 nRW;
u32 DataOut;
u8 AddressOut;
u8 Ready;
u32 DataIn;
u8 AddressIn;
arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
{size_t i;
for (i = 0; i < count + 1; i++)
{
if (i < count)
{
nRW = actions[i].write ? 1 : 0;
DataOut = actions[i].value;
AddressOut = actions[i].address;
}
else
{
nRW = 0;
DataOut = 0;
AddressOut = 0;
}
do
{
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
jtag_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_PD);
jtag_execute_queue();
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
}
while (!Ready); /* 'nRW' is 'Ready' on read out */
if (i > 0)
{
if (actions[i - 1].address != AddressIn)
{
WARNING("Scan chain 7 shifted out unexpected address");
}
if (!actions[i - 1].write)
{
actions[i - 1].value = DataIn;
}
else
{
if (actions[i - 1].value != DataIn)
{
WARNING("Scan chain 7 shifted out unexpected data");
}
}
}
}}
{size_t i;
for (i = 0; i < count; i++)
{
JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
}}
}
void arm11_sc7_clear_bw(arm11_common_t * arm11)
{
size_t actions = arm11->brp + arm11->wrp;
arm11_sc7_action_t clear_bw[actions];
{size_t i;
for (i = 0; i < actions; i++)
{
clear_bw[i].write = true;
clear_bw[i].value = 0;
clear_bw[i].address =
i < arm11->brp ?
ARM11_SC7_BCR0 + i :
ARM11_SC7_WCR0 + i - arm11->brp;
}}
arm11_sc7_run(arm11, clear_bw, actions);
}

2
src/target/arm720t.c
View File

@ -127,7 +127,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
jtag_add_dr_scan(2, fields, -1, NULL);
jtag_add_dr_scan(2, fields, -1);
if (clock)
jtag_add_runtest(0, -1);

10
src/target/arm7tdmi.c
View File

@ -129,7 +129,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
arm_jtag_scann(&arm7_9->jtag_info, 0x1);
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(2, fields, TAP_PD, NULL);
jtag_add_dr_scan(2, fields, TAP_PD);
jtag_execute_queue();
fields[0].in_value = NULL;
@ -137,7 +137,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
fields[1].in_value = NULL;
fields[1].out_value = databus;
jtag_add_dr_scan(2, fields, TAP_PD, NULL);
jtag_add_dr_scan(2, fields, TAP_PD);
if (breakpoint & 1)
target->debug_reason = DBG_REASON_WATCHPOINT;
@ -190,7 +190,7 @@ int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *in, int breakpoint)
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
jtag_add_dr_scan(2, fields, -1, NULL);
jtag_add_dr_scan(2, fields, -1);
jtag_add_runtest(0, -1);
@ -239,7 +239,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
jtag_add_dr_scan(2, fields, -1, NULL);
jtag_add_dr_scan(2, fields, -1);
jtag_add_runtest(0, -1);
@ -304,7 +304,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
jtag_add_dr_scan(2, fields, -1, NULL);
jtag_add_dr_scan(2, fields, -1);
jtag_add_runtest(0, -1);

8
src/target/arm920t.c
View File

@ -148,12 +148,12 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
jtag_add_dr_scan(4, fields, -1, NULL);
jtag_add_dr_scan(4, fields, -1);
fields[1].in_handler_priv = value;
fields[1].in_handler = arm_jtag_buf_to_u32;
jtag_add_dr_scan(4, fields, -1, NULL);
jtag_add_dr_scan(4, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
jtag_execute_queue();
@ -220,7 +220,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
jtag_add_dr_scan(4, fields, -1, NULL);
jtag_add_dr_scan(4, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
@ -286,7 +286,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
jtag_add_dr_scan(4, fields, -1, NULL);
jtag_add_dr_scan(4, fields, -1);
arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);

8
src/target/arm926ejs.c
View File

@ -173,7 +173,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
jtag_add_dr_scan(4, fields, -1, NULL);
jtag_add_dr_scan(4, fields, -1);
fields[0].in_handler_priv = value;
fields[0].in_handler = arm_jtag_buf_to_u32;
@ -183,7 +183,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, -1, NULL);
jtag_add_dr_scan(4, fields, -1);
jtag_execute_queue();
} while (buf_get_u32(&access, 0, 1) != 1);
@ -255,14 +255,14 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
jtag_add_dr_scan(4, fields, -1, NULL);
jtag_add_dr_scan(4, fields, -1);
do
{
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, -1, NULL);
jtag_add_dr_scan(4, fields, -1);
jtag_execute_queue();
} while (buf_get_u32(&access, 0, 1) != 1);

6
src/target/arm966e.c
View File

@ -225,12 +225,12 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
fields[0].in_handler_priv = value;
fields[0].in_handler = arm_jtag_buf_to_u32;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
jtag_execute_queue();
@ -286,7 +286,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);

10
src/target/arm9tdmi.c
View File

@ -151,7 +151,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
arm_jtag_scann(&arm7_9->jtag_info, 0x1);
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(3, fields, TAP_PD, NULL);
jtag_add_dr_scan(3, fields, TAP_PD);
jtag_execute_queue();
fields[0].in_value = NULL;
@ -161,7 +161,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
fields[2].in_value = NULL;
fields[2].out_value = instructionbus;
jtag_add_dr_scan(3, fields, TAP_PD, NULL);
jtag_add_dr_scan(3, fields, TAP_PD);
if (debug_reason & 0x4)
if (debug_reason & 0x2)
@ -234,7 +234,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
jtag_add_runtest(0, -1);
@ -294,7 +294,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
jtag_add_runtest(0, -1);
@ -370,7 +370,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
jtag_add_runtest(0, -1);

4
src/target/arm_jtag.c
View File

@ -51,7 +51,7 @@ int arm_jtag_set_instr(arm_jtag_t *jtag_info, u32 new_instr, in_handler_t handl
field.in_check_mask = NULL;
field.in_handler = handler;
field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, -1, NULL);
jtag_add_ir_scan(1, &field, -1);
free(field.out_value);
@ -84,7 +84,7 @@ int arm_jtag_scann(arm_jtag_t *jtag_info, u32 new_scan_chain)
arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL);
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
jtag_info->cur_scan_chain = new_scan_chain;

4
src/target/cortex_swjdp.c
View File

@ -87,7 +87,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
jtag_add_dr_scan(2, fields, -1, NULL);
jtag_add_dr_scan(2, fields, -1);
return ERROR_OK;
}
@ -132,7 +132,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
jtag_add_dr_scan(2, fields, -1, NULL);
jtag_add_dr_scan(2, fields, -1);
return ERROR_OK;
}

16
src/target/embeddedice.c
View File

@ -256,7 +256,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
fields[0].in_value = reg->value;
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
@ -267,7 +267,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
*/
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
return ERROR_OK;
}
@ -318,7 +318,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
while (size > 0)
{
@ -330,7 +330,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
fields[0].in_handler = arm_jtag_buf_to_u32;
fields[0].in_handler_priv = data;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
data++;
size--;
@ -420,7 +420,7 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
return ERROR_OK;
}
@ -480,7 +480,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
while (size > 0)
{
buf_set_u32(fields[0].out_value, 0, 32, *data);
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
data++;
size--;
@ -546,11 +546,11 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
gettimeofday(&lap, NULL);
do
{
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;

14
src/target/etb.c
View File

@ -79,7 +79,7 @@ int etb_set_instr(etb_t *etb, u32 new_instr)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, -1, NULL);
jtag_add_ir_scan(1, &field, -1);
free(field.out_value);
}
@ -106,7 +106,7 @@ int etb_scann(etb_t *etb, u32 new_scan_chain)
/* select INTEST instruction */
etb_set_instr(etb, 0x2);
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
etb->cur_scan_chain = new_scan_chain;
@ -215,7 +215,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
fields[0].in_handler = buf_to_u32_handler;
@ -231,7 +231,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
buf_set_u32(fields[1].out_value, 0, 7, 0);
fields[0].in_handler_priv = &data[i];
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
}
jtag_execute_queue();
@ -286,7 +286,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
/* read the identification register in the second run, to make sure we
* don't read the ETB data register twice, skipping every second entry
@ -296,7 +296,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
free(fields[1].out_value);
free(fields[2].out_value);
@ -381,7 +381,7 @@ int etb_write_reg(reg_t *reg, u32 value)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
free(fields[0].out_value);
free(fields[1].out_value);

6
src/target/etm.c
View File

@ -356,12 +356,12 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
fields[0].in_value = reg->value;
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
free(fields[1].out_value);
free(fields[2].out_value);
@ -446,7 +446,7 @@ int etm_write_reg(reg_t *reg, u32 value)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
free(fields[0].out_value);
free(fields[1].out_value);

26
src/target/xscale.c
View File

@ -226,7 +226,7 @@ int xscale_jtag_set_instr(int chain_pos, u32 new_instr)
field.in_value = NULL;
jtag_set_check_value(&field, device->expected, device->expected_mask, NULL);
jtag_add_ir_scan(1, &field, -1, NULL);
jtag_add_ir_scan(1, &field, -1);
free(field.out_value);
}
@ -300,7 +300,7 @@ int xscale_read_dcsr(target_t *target)
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -320,7 +320,7 @@ int xscale_read_dcsr(target_t *target)
jtag_add_end_state(TAP_RTI);
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
return ERROR_OK;
}
@ -392,7 +392,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
fields[1].in_handler_priv = (u8*)&field1[i];
jtag_add_pathmove(3, path);
jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
jtag_add_dr_scan(3, fields, TAP_RTI);
words_scheduled++;
}
@ -513,7 +513,7 @@ int xscale_read_tx(target_t *target, int consume)
else
jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
jtag_add_dr_scan(3, fields, TAP_RTI);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -589,7 +589,7 @@ int xscale_write_rx(target_t *target)
DEBUG("polling RX");
do
{
jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
jtag_add_dr_scan(3, fields, TAP_RTI);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -607,7 +607,7 @@ int xscale_write_rx(target_t *target)
/* set rx_valid */
field2 = 0x1;
jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
jtag_add_dr_scan(3, fields, TAP_RTI);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -692,7 +692,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
output[2]=buffer[1];
output[3]=buffer[0];
}
jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
jtag_add_dr_scan(3, fields, TAP_RTI);
buffer += size;
}
@ -716,7 +716,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
exit(-1);
}
jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
jtag_add_dr_scan(3, fields, TAP_RTI);
buffer += size;
}
@ -793,7 +793,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_dr_scan(3, fields, -1);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -865,7 +865,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
jtag_add_dr_scan(2, fields, -1, NULL);
jtag_add_dr_scan(2, fields, -1);
fields[0].num_bits = 32;
fields[0].out_value = packet;
@ -877,7 +877,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
{
buf_set_u32(packet, 0, 32, buffer[word]);
cmd = parity(*((u32*)packet));
jtag_add_dr_scan(2, fields, -1, NULL);
jtag_add_dr_scan(2, fields, -1);
}
jtag_execute_queue();
@ -923,7 +923,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
jtag_add_dr_scan(2, fields, -1, NULL);
jtag_add_dr_scan(2, fields, -1);
return ERROR_OK;
}

16
src/xsvf/xsvf.c
View File

@ -188,9 +188,9 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_handler = NULL;
field.in_handler_priv = NULL;
if (device == -1)
jtag_add_plain_ir_scan(1, &field, TAP_PI, NULL);
jtag_add_plain_ir_scan(1, &field, TAP_PI);
else
jtag_add_ir_scan(1, &field, TAP_PI, NULL);
jtag_add_ir_scan(1, &field, TAP_PI);
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
@ -228,9 +228,9 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
if (device == -1)
jtag_add_plain_dr_scan(1, &field, TAP_PD, NULL);
jtag_add_plain_dr_scan(1, &field, TAP_PD);
else
jtag_add_dr_scan(1, &field, TAP_PD, NULL);
jtag_add_dr_scan(1, &field, TAP_PD);
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
@ -302,9 +302,9 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
if (device == -1)
jtag_add_plain_dr_scan(1, &field, TAP_PD, NULL);
jtag_add_plain_dr_scan(1, &field, TAP_PD);
else
jtag_add_dr_scan(1, &field, TAP_PD, NULL);
jtag_add_dr_scan(1, &field, TAP_PD);
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
@ -428,9 +428,9 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_handler = NULL;
field.in_handler_priv = NULL;
if (device == -1)
jtag_add_plain_ir_scan(1, &field, xsvf_to_tap[xendir], NULL);
jtag_add_plain_ir_scan(1, &field, xsvf_to_tap[xendir]);
else
jtag_add_ir_scan(1, &field, xsvf_to_tap[xendir], NULL);
jtag_add_ir_scan(1, &field, xsvf_to_tap[xendir]);
}
free(ir_buf);
}