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David Brownell <david-b@pacbell.net> More instruction decoding fixes based on test cases, covering 

ARMv7-M arch manual:

 A5.3.1 Data processing (modified immediate)
 A5.3.3 Data processing (plain binary immediate)
 A5.3.4 Branches and miscellaneous control

and other (immediate) encodings referenced there.  Several of
these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but
there were a few bugs too.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
oharboe 2009-07-24 16:49:44 +00:00
parent ad3a24f944
commit 67dbf35896
1 changed files with 10 additions and 9 deletions
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19
src/target/arm_disassembler.c
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@ -1644,7 +1644,7 @@ int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
break; break;
case 0x9: case 0x9:
instruction->type = ARM_RSB; instruction->type = ARM_RSB;
mnemonic = "NEGS"; mnemonic = "RSBS";
instruction->info.data_proc.variant = 0 /*immediate*/; instruction->info.data_proc.variant = 0 /*immediate*/;
instruction->info.data_proc.shifter_operand.immediate.immediate = 0; instruction->info.data_proc.shifter_operand.immediate.immediate = 0;
instruction->info.data_proc.Rn = Rm; instruction->info.data_proc.Rn = Rm;
@ -2600,7 +2600,6 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
mnemonic = "TST"; mnemonic = "TST";
one = true; one = true;
suffix = ""; suffix = "";
suffix2 = ".W";
rd = rn; rd = rn;
} else { } else {
instruction->type = ARM_AND; instruction->type = ARM_AND;
@ -2660,6 +2659,7 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
case 10: case 10:
instruction->type = ARM_ADC; instruction->type = ARM_ADC;
mnemonic = "ADC"; mnemonic = "ADC";
suffix2 = ".W";
break; break;
case 11: case 11:
instruction->type = ARM_SBC; instruction->type = ARM_SBC;
@ -2708,8 +2708,8 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
bool add = false; bool add = false;
bool is_signed = false; bool is_signed = false;
immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 12); immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 4);
if (opcode & (1 << 27)) if (opcode & (1 << 26))
immed |= (1 << 11); immed |= (1 << 11);
switch ((opcode >> 20) & 0x1f) { switch ((opcode >> 20) & 0x1f) {
@ -2718,15 +2718,16 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
add = true; add = true;
goto do_adr; goto do_adr;
} }
mnemonic = "ADD.W"; mnemonic = "ADDW";
break; break;
case 4: case 4:
mnemonic = "MOV.W"; immed |= (opcode >> 4) & 0xf000;
break; sprintf(cp, "MOVW\tr%d, #%d\t; %#3.3x", rd, immed, immed);
return ERROR_OK;
case 0x0a: case 0x0a:
if (rn == 0xf) if (rn == 0xf)
goto do_adr; goto do_adr;
mnemonic = "SUB.W"; mnemonic = "SUBW";
break; break;
case 0x0c: case 0x0c:
/* move constant to top 16 bits of register */ /* move constant to top 16 bits of register */
@ -2743,7 +2744,7 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
immed |= (opcode >> 10) & 0x1c; immed |= (opcode >> 10) & 0x1c;
sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t", sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t",
is_signed ? "S" : "U", is_signed ? "S" : "U",
rd, (int) (opcode & 0x1f) + 1, rn, rd, (int) (opcode & 0x1f) + is_signed, rn,
(opcode & (1 << 21)) ? "ASR" : "LSL", (opcode & (1 << 21)) ? "ASR" : "LSL",
immed ? immed : 32); immed ? immed : 32);
return ERROR_OK; return ERROR_OK;