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Memory read/write works if the core can keep up. 

Change-Id: Ieca50ece266fbc9d2ff16a5cc2e6b4b926ad5e6f
macbuild
Tim Newsome 2017-10-17 11:52:07 -07:00
parent fbe2980eb7
commit 65be0776d8
1 changed files with 8 additions and 11 deletions
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19
src/target/riscv/riscv-013.c
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@ -1388,18 +1388,15 @@ static int read_memory(struct target *target, target_addr_t address,
// Now read whatever we got out of the batch. // Now read whatever we got out of the batch.
unsigned rereads = 0; unsigned rereads = 0;
for (riscv_addr_t addr = cur_addr - size; addr < next_addr - size; addr += size) { for (riscv_addr_t addr = cur_addr - size; addr < next_addr - size; addr += size) {
if (addr < address) if (addr >= address) {
continue; riscv_addr_t offset = addr - address;
uint64_t dmi_out = riscv_batch_get_dmi_read(batch, rereads);
riscv_addr_t offset = addr - address; uint32_t value = get_field(dmi_out, DTM_DMI_DATA);
write_to_buf(buffer + offset, value, size);
uint64_t dmi_out = riscv_batch_get_dmi_read(batch, rereads); LOG_DEBUG("M[0x%" TARGET_PRIxADDR "] reads 0x%08x", addr, value);
uint32_t value = get_field(dmi_out, DTM_DMI_DATA); }
write_to_buf(buffer + offset, value, size);
rereads++; rereads++;
LOG_DEBUG("M[0x%" TARGET_PRIxADDR "] reads 0x%08x", addr, value);
} }
riscv_batch_free(batch); riscv_batch_free(batch);
@ -1512,6 +1509,7 @@ static int write_memory(struct target *target, target_addr_t address,
} }
LOG_DEBUG("M[0x%08" PRIx64 "] writes 0x%08x", address + offset, value); LOG_DEBUG("M[0x%08" PRIx64 "] writes 0x%08x", address + offset, value);
cur_addr += size;
if (setup_needed) { if (setup_needed) {
if (register_write_direct(target, GDB_REGNO_S0, if (register_write_direct(target, GDB_REGNO_S0,
@ -1541,7 +1539,6 @@ static int write_memory(struct target *target, target_addr_t address,
if (riscv_batch_full(batch)) if (riscv_batch_full(batch))
break; break;
} }
cur_addr += size;
} }
riscv_batch_run(batch); riscv_batch_run(batch);