michal smulski <michal.smulski@ooma.com> reset now works
git-svn-id: svn://svn.berlios.de/openocd/trunk@2778 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
oharboe
parent
e4de4251fe
commit
642519649e
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@ -1,33 +1,34 @@
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source [find target/c100.cfg]
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source [find c100.cfg]
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# basic register defintion for C100
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source [find target/c100regs.tcl]
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source [find c100regs.tcl]
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# board-config info
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source [find target/c100config.tcl]
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source [find c100config.tcl]
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# C100 helper functions
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source [find target/c100helper.tcl]
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source [find c100helper.tcl]
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# Telo board & C100 support trst and srst
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# however openocd does not support
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# 1. setting srst reset pulse width
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# 2. setting delay between srst pulse and JTAG access
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# This really makes the srst useless for now.
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# Note that libftd2xx.so tries to assert srst
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# which break this script
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# use libftdi.so library instead with this script
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# make the reset asserted to
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# allow RC circuit to discharge for: [ms]
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jtag_nsrst_assert_width 100
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jtag_ntrst_assert_width 100
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# don't talk to JTAG after reset for: [ms]
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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reset_config trst_and_srst separate
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# issue telnet: reset init
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# issue gdb: monitor reset init
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$_TARGETNAME configure -event reset-init {
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jtag_khz 100
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# setup GPIO used as control signals for C100
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setupGPIO
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# This will allow acces to lower 8MB or NOR
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lowGPIO5
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# setup NOR size,timing,etc.
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setupNOR
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# setup internals + PLL + DDR2
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initC100
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# this will setup Telo board
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setupTelo
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#turn up the JTAG speed
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jtag_khz 3000
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puts "JTAG speek now 3MHz"
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@ -38,10 +39,15 @@ $_TARGETNAME configure -event reset-deassert-post {
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# Force target into ARM state.
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# soft_reset_halt # not implemented on ARM11
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puts "Detected SRSRT asserted on C100.CPU"
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}
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proc power_restore {} { puts "Sensed power restore. No action." }
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$_TARGETNAME configure -event reset-assert-post {
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puts "Assering reset"
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#sleep 10
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}
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proc power_restore {} { puts "Sensed power restore. No action." }
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proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
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@ -3,7 +3,7 @@
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# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
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proc config {label} {
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return [dict get [configC100] $label ]
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return [dict get [configC100] $label ]
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}
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# show the value for the param. with label
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@ -15,7 +15,7 @@ proc showconfig {label} {
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# when there are more then one board config
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# use soft links to c100board-config.tcl
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# so that only the right board-config gets
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# included (just like include/configs/board-configs.h
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# included (just like include/configs/board-configs.h
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# in u-boot.
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proc configC100 {} {
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# xtal freq. 24MHz
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@ -28,7 +28,7 @@ proc configC100 {} {
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# y = amba_clk * (w+1)*(x+1)*2/xtal_clk
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dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
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# Arm Clk 450MHz, must be a multiple of 25 MHz
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# Arm Clk 450MHz, must be a multiple of 25 MHz
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dict set configC100 CFG_ARM_CLOCK 450000000
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dict set configC100 w_arm 0
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dict set configC100 x_arm 1
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@ -38,20 +38,34 @@ proc configC100 {} {
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}
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# This should be called for reset init event handler
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proc setupTelo {} {
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# setup GPIO used as control signals for C100
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setupGPIO
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# This will allow acces to lower 8MB or NOR
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lowGPIO5
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# setup NOR size,timing,etc.
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setupNOR
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# setup internals + PLL + DDR2
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initC100
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}
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proc setupNOR {} {
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puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
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# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
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set EX_CSEN_REG [regs EX_CSEN_REG ]
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set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
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set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
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set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
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set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
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set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
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set EX_CSEN_REG [regs EX_CSEN_REG ]
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set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
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set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
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set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
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set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
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set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
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set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
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set EX_MFSM_REG [regs EX_MFSM_REG ]
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set EX_CSFSM_REG [regs EX_CSFSM_REG ]
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set EX_WRFSM_REG [regs EX_WRFSM_REG ]
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set EX_RDFSM_REG [regs EX_RDFSM_REG ]
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set EX_MFSM_REG [regs EX_MFSM_REG ]
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set EX_CSFSM_REG [regs EX_CSFSM_REG ]
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set EX_WRFSM_REG [regs EX_WRFSM_REG ]
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set EX_RDFSM_REG [regs EX_RDFSM_REG ]
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# enable Expansion Bus Clock + CS0 (NOR)
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mww $EX_CSEN_REG 0x3
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@ -62,7 +76,7 @@ proc setupNOR {} {
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# set timings to NOR
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mww $EX_CS0_TMG1_REG 0x03034006
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mww $EX_CS0_TMG2_REG 0x04040002
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#mww $EX_CS0_TMG3_REG
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#mww $EX_CS0_TMG3_REG
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# set EBUS clock 165/5=33MHz
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mww $EX_CLOCK_DIV_REG 0x5
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# everthing else is OK with default
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@ -72,7 +86,7 @@ proc bootNOR {} {
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set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
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set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
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set DDR_RST [regs DDR_RST]
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# put DDR controller in reset (so that it comes reset in u-boot)
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mmw $BLOCK_RESET_REG 0x0 $DDR_RST
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# setup CS0 controller for NOR
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@ -93,8 +107,8 @@ proc setupGPIO {} {
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#GPIO17 reset for DECT module.
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#GPIO29 CS_n for NAND
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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set GPIO_OE_REG [regs GPIO_OE_REG]
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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set GPIO_OE_REG [regs GPIO_OE_REG]
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# set GPIO29=GPIO17=1, GPIO5=0
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mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
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@ -104,14 +118,14 @@ proc setupGPIO {} {
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proc highGPIO5 {} {
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puts "GPIO5 high"
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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# set GPIO5=1
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mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
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}
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proc lowGPIO5 {} {
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puts "GPIO5 low"
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
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# set GPIO5=0
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mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
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}
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@ -119,31 +133,32 @@ proc lowGPIO5 {} {
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proc boardID {id} {
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# so far built:
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# 4'b1111
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dict set boardID 15 name "EVT1"
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dict set boardID 15 name "EVT1"
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dict set boardID 15 ddr2size 128M
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# dict set boardID 15 nandsize 1G
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# dict set boardID 15 norsize 16M
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# 4'b0000
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dict set boardID 0 name "EVT2"
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dict set boardID 0 name "EVT2"
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dict set boardID 0 ddr2size 128M
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# 4'b0001
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dict set boardID 1 name "EVT3"
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dict set boardID 1 name "EVT3"
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dict set boardID 1 ddr2size 256M
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# 4'b1110
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dict set boardID 14 name "EVT3_old"
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dict set boardID 14 ddr2size 128M
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# 4'b0010
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dict set boardID 2 name "EVT4"
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dict set boardID 2 name "EVT4"
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dict set boardID 2 ddr2size 256M
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return $boardID
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}
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# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
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# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
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# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
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proc ooma_board_detect {} {
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set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
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# read the current value of the BOOTSRAP pins
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set tmp [mrw $GPIO_BOOTSTRAP_REG]
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puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
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@ -152,12 +167,77 @@ proc ooma_board_detect {} {
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# display board ID
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puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
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# show it on serial console
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putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
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# return the ddr2 size, used to configure DDR2 on a given board.
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return [dict get [boardID $gpbt] $gpbt ddr2size]
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}
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proc configureDDR2regs_256M {} {
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puts "ConfigureDDR2regs_256M TBD"
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set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
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set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
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set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
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set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
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set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
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set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
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set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
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set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
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set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
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set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
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set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
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set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
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set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
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set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
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set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
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set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
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set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
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set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
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set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
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set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
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set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
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set DENALI_CTL_02_VAL 0x0100000000010100
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set DENALI_CTL_11_VAL 0x433a32164a560a00
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mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
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# 01_DATA mod [40]=1, enable BA2
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mw64bit $DENALI_CTL_01_DATA 0x0100010100000001
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mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
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mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
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mw64bit $DENALI_CTL_04_DATA 0x0000010100000001
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mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
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mw64bit $DENALI_CTL_06_DATA 0x060a020200020202
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mw64bit $DENALI_CTL_07_DATA 0x0000000300000206
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mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209
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mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a
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mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18
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# 11_DATA mod [39-32]=16,more refresh
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mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
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mw64bit $DENALI_CTL_12_DATA 0x0000000000000800
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mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
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mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
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mw64bit $DENALI_CTL_15_DATA 0x04f8000000000000
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mw64bit $DENALI_CTL_16_DATA 0x000000002cca0000
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mw64bit $DENALI_CTL_17_DATA 0x0000000000000000
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mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
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mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600
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mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8
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set wr_dqs_shift 0x40
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# start DDRC
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mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
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# wait int_status[2] (DRAM init complete)
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puts -nonewline "Waiting for DDR2 controller to init..."
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
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while { [expr $tmp & 0x040000] == 0 } {
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sleep 1
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
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}
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puts "done."
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# do ddr2 training sequence
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# TBD (for now, if you need it, run trainDDR command)
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}
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# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
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@ -187,9 +267,9 @@ proc configureDDR2regs_128M {} {
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set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
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set DENALI_CTL_02_VAL 0x0100010000010100
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set DENALI_CTL_02_VAL 0x0100010000010100
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set DENALI_CTL_11_VAL 0x433A42124A650A37
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# set some default values
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# set some default values
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mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
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mw64bit $DENALI_CTL_01_DATA 0x0100000100000101
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mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
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@ -218,11 +298,12 @@ proc configureDDR2regs_128M {} {
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# wait int_status[2] (DRAM init complete)
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puts -nonewline "Waiting for DDR2 controller to init..."
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
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while { [expr $tmp & 0x040000] == 0 } {
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while { [expr $tmp & 0x040000] == 0 } {
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sleep 1
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
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}
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mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
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# This is not necessary
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#mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
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puts "done."
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# do ddr2 training sequence
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@ -237,18 +318,18 @@ proc setupUART0 {} {
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set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
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set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
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set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0]
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set UART0_LCR [regs UART0_LCR]
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set LCR_DLAB [regs LCR_DLAB]
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set UART0_DLL [regs UART0_DLL]
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set UART0_DLH [regs UART0_DLH]
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set UART0_IIR [regs UART0_IIR]
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set UART0_IER [regs UART0_IER]
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set LCR_ONE_STOP [regs LCR_ONE_STOP]
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set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
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set UART0_LCR [regs UART0_LCR]
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set LCR_DLAB [regs LCR_DLAB]
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set UART0_DLL [regs UART0_DLL]
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set UART0_DLH [regs UART0_DLH]
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set UART0_IIR [regs UART0_IIR]
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set UART0_IER [regs UART0_IER]
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set LCR_ONE_STOP [regs LCR_ONE_STOP]
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set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
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set FCR_XMITRES [regs FCR_XMITRES]
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set FCR_RCVRRES [regs FCR_RCVRRES]
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set FCR_FIFOEN [regs FCR_FIFOEN]
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set IER_UUE [regs IER_UUE]
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set FCR_RCVRRES [regs FCR_RCVRRES]
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set FCR_FIFOEN [regs FCR_FIFOEN]
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set IER_UUE [regs IER_UUE]
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# unlock writing to IOCTRL register
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mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
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@ -274,7 +355,7 @@ proc setupUART0 {} {
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proc putcUART0 {char} {
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set UART0_LSR [regs UART0_LSR]
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set UART0_LSR [regs UART0_LSR]
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set UART0_THR [regs UART0_THR]
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set LSR_TEMT [regs LSR_TEMT]
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@ -308,17 +389,24 @@ proc trainDDR2 {} {
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resume
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}
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proc flashUBOOT {} {
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proc flashUBOOT {file} {
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# this will update uboot on NOR partition
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set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
|
||||
|
||||
|
||||
# setup CS0 controller for NOR
|
||||
setupNOR
|
||||
# make sure we are accessing the lower part of NOR
|
||||
lowGPIO5
|
||||
flash probe 0
|
||||
puts "Erasing sectors 0-3 for uboot"
|
||||
putsUART0 "Erasing sectors 0-3 for uboot\n"
|
||||
flash erase_sector 0 0 3
|
||||
puts "Programming u-boot, takes about 4-5 min for 256kb"
|
||||
flash write_image ./images/u-boot.bin $EXP_CS0_BASEADDR
|
||||
puts "Programming u-boot"
|
||||
putsUART0 "Programming u-boot..."
|
||||
memwrite burst enable
|
||||
flash write_image $file $EXP_CS0_BASEADDR
|
||||
memwrite burst disable
|
||||
putsUART0 "done.\n"
|
||||
putsUART0 "Rebooting, please wait!\n"
|
||||
reboot
|
||||
}
|
||||
|
|
@ -1,9 +1,60 @@
|
|||
source [find c100.cfg]
|
||||
# basic register defintion for C100
|
||||
source [find c100regs.tcl]
|
||||
# board-config info
|
||||
source [find c100config.tcl]
|
||||
# C100 helper functions
|
||||
source [find c100helper.tcl]
|
||||
|
||||
|
||||
# Telo board & C100 support trst and srst
|
||||
# Note that libftd2xx.so tries to assert srst
|
||||
# which break this script
|
||||
# use libftdi.so library instead with this script
|
||||
# make the reset asserted to
|
||||
# allow RC circuit to discharge for: [ms]
|
||||
jtag_nsrst_assert_width 100
|
||||
jtag_ntrst_assert_width 100
|
||||
# don't talk to JTAG after reset for: [ms]
|
||||
jtag_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
reset_config trst_and_srst separate
|
||||
|
||||
|
||||
|
||||
|
||||
# issue telnet: reset init
|
||||
# issue gdb: monitor reset init
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
jtag_khz 100
|
||||
# this will setup Telo board
|
||||
setupTelo
|
||||
#turn up the JTAG speed
|
||||
jtag_khz 3000
|
||||
puts "JTAG speek now 3MHz"
|
||||
puts "type helpC100 to get help on C100"
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-deassert-post {
|
||||
# Force target into ARM state.
|
||||
# soft_reset_halt # not implemented on ARM11
|
||||
puts "Detected SRSRT asserted on C100.CPU"
|
||||
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-assert-post {
|
||||
puts "Assering reset"
|
||||
#sleep 10
|
||||
}
|
||||
|
||||
proc power_restore {} { puts "Sensed power restore. No action." }
|
||||
proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
|
||||
|
||||
|
||||
# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
|
||||
# it's really 16MB but the upper 8mb is controller via gpio?
|
||||
# it's really 16MB but the upper 8mb is controller via gpio
|
||||
# openocd does not support 'complex reads/writes' to NOR
|
||||
flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
|
||||
|
||||
#
|
||||
gdb_memory_map enable
|
||||
|
||||
# writing data to memory does not work without this
|
||||
memwrite burst disable
|
||||
Loading…
Reference in New Issue