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armv7a_mmu: Remove armv7a_mmu_translate_va() 

This function is not used anywhere in the tree, remove it, such that we
only have a single function moving forward that might need to deal with
short vs. long format specifics.

Change-Id: I80e81cd7eba1e028d1afaeaedb675b46c0ca6fa1
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-on: http://openocd.zylin.com/5213
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
bscan_optimization
Florian Fainelli 2019-06-05 12:37:13 -07:00 committed by Matthias Welwarsky
parent ba11adb833
commit 604dded6f1
2 changed files with 0 additions and 87 deletions
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86
src/target/armv7a_mmu.c
View File

@ -34,92 +34,6 @@
#define SCTLR_BIT_AFE (1 << 29)
/* method adapted to Cortex-A : reused ARM v4 v5 method */
int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
{
uint32_t first_lvl_descriptor = 0x0;
uint32_t second_lvl_descriptor = 0x0;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
uint32_t ttbidx = 0; /* default to ttbr0 */
uint32_t ttb_mask;
uint32_t va_mask;
uint32_t ttb;
if (target->state != TARGET_HALTED)
LOG_INFO("target not halted, using cached values for translation table!");
/* if va is above the range handled by ttbr0, select ttbr1 */
if (va > armv7a->armv7a_mmu.ttbr_range[0]) {
/* select ttb 1 */
ttbidx = 1;
}
ttb = armv7a->armv7a_mmu.ttbr[ttbidx];
ttb_mask = armv7a->armv7a_mmu.ttbr_mask[ttbidx];
va_mask = 0xfff00000 & armv7a->armv7a_mmu.ttbr_range[ttbidx];
LOG_DEBUG("ttb_mask %" PRIx32 " va_mask %" PRIx32 " ttbidx %i",
ttb_mask, va_mask, ttbidx);
retval = armv7a->armv7a_mmu.read_physical_memory(target,
(ttb & ttb_mask) | ((va & va_mask) >> 18),
4, 1, (uint8_t *)&first_lvl_descriptor);
if (retval != ERROR_OK)
return retval;
first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
&first_lvl_descriptor);
/* reuse armv4_5 piece of code, specific armv7a changes may come later */
LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
if ((first_lvl_descriptor & 0x3) == 0) {
/* Avoid LOG_ERROR, probably GDB is guessing the stack frame */
LOG_WARNING("Address translation failure [1]: va %8.8" PRIx32 "", va);
return ERROR_TARGET_TRANSLATION_FAULT;
}
if ((first_lvl_descriptor & 0x40002) == 2) {
/* section descriptor */
*val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
return ERROR_OK;
} else if ((first_lvl_descriptor & 0x40002) == 0x40002) {
/* supersection descriptor */
if (first_lvl_descriptor & 0x00f001e0) {
LOG_ERROR("Physical address does not fit into 32 bits");
return ERROR_TARGET_TRANSLATION_FAULT;
}
*val = (first_lvl_descriptor & 0xff000000) | (va & 0x00ffffff);
return ERROR_OK;
}
/* page table */
retval = armv7a->armv7a_mmu.read_physical_memory(target,
(first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
4, 1, (uint8_t *)&second_lvl_descriptor);
if (retval != ERROR_OK)
return retval;
second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
&second_lvl_descriptor);
LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
if ((second_lvl_descriptor & 0x3) == 0) {
/* Avoid LOG_ERROR, probably GDB is guessing the stack frame */
LOG_WARNING("Address translation failure [2]: va %8.8" PRIx32 "", va);
return ERROR_TARGET_TRANSLATION_FAULT;
}
if ((second_lvl_descriptor & 0x3) == 1) {
/* large page descriptor */
*val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
} else {
/* small page descriptor */
*val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
}
return ERROR_OK;
}
/* V7 method VA TO PA */
int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
uint32_t *val, int meminfo)

1
src/target/armv7a_mmu.h
View File

@ -19,7 +19,6 @@
#ifndef OPENOCD_TARGET_ARMV7A_MMU_H
#define OPENOCD_TARGET_ARMV7A_MMU_H
extern int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
extern int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
uint32_t *val, int meminfo);