From 5d43ffd5bc0ca281314f5ccda417cc7144c31144 Mon Sep 17 00:00:00 2001 From: James Robinson Date: Sat, 4 Feb 2012 21:06:42 -0500 Subject: [PATCH] topic: Add support for i.MX28EVK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added the file imx28.cfg to the target directory Added the file imx28evk.cfg to the board directory Change-Id: I02a74a03f3773892f830d13660ffdded34f3261d Signed-off-by: James Robinson Reviewed-on: http://openocd.zylin.com/428 Tested-by: jenkins Reviewed-by: Øyvind Harboe Reviewed-by: Spencer Oliver --- tcl/board/imx28evk.cfg | 168 +++++++++++++++++++++++++++++++++++++++++ tcl/target/imx28.cfg | 38 ++++++++++ 2 files changed, 206 insertions(+) create mode 100644 tcl/board/imx28evk.cfg create mode 100644 tcl/target/imx28.cfg diff --git a/tcl/board/imx28evk.cfg b/tcl/board/imx28evk.cfg new file mode 100644 index 000000000..a85c2ca67 --- /dev/null +++ b/tcl/board/imx28evk.cfg @@ -0,0 +1,168 @@ +# The IMX28EVK eval board has a IMX28 chip +# Tested on SCH-26241 Rev D board with Olimex ARM-USB-OCD +# Date: 201-02-01 +# Authors: James Robinson & Fabio Estevam + +source [find target/imx28.cfg] +$_TARGETNAME configure -event gdb-attach { imx28evk_init } +$_TARGETNAME configure -event reset-init { imx28evk_init } + +proc imx28evk_init { } { + + halt + + #**************************** + # VDDD setting + #**************************** + # set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e + mww 0x80044010 0x0003F503 + mww 0x80044040 0x0002041E + + #**************************** + # CLOCK set up + #**************************** + # Power up PLL0 HW_CLKCTRL_PLL0CTRL0 + mww 0x80040000 0x00020000 + # Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0 + # EMI - first set DIV_EMI to div-by-2 before programming frac divider + mww 0x800400F0 0x80000002 + + + # CPU: CPUFRAC=19 480*18/29=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz + mww 0x800401B0 0x92921613 + # Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR + mww 0x800401D8 0x00040080 + # HCLK = 227MHz,HW_CLKCTRL_HBUS DIV =0x2 + mww 0x80040060 0x00000002 + + #**************************** + # POWER up DCDD_VDDA (DDR2) + #**************************** + # Now set the voltage level to 1.8V HW_POWER_VDDACTRL bits TRC=0xC + mww 0x80044050 0x0000270C + + #**************************** + # DDR2 DCDD_VDDA + #**************************** + # First set up pin muxing and drive strength + # Ungate module clock and bring out of reset HW_PINCTRL_CTRL_CLR + mww 0x80018008 0xC0000000 + + #**************************** + # EMI PAD setting + #**************************** + # Set up drive strength for EMI pins + mww 0x80019B80 0x00030000 + #IOMUXC_SW_PAD_CTL_GRP_CTLDS + + # Set up pin muxing for EMI, HW_PINCTRL_MUXSEL10, 11, 12, 13 + mww 0x800181A8 0xFFFFFFFF + mww 0x800181B8 0xFFFFFFFF + mww 0x800181C8 0xFFFFFFFF + mww 0x800181D8 0xFFFFFFFF + + #** Ungate EMI clock in CCM + mww 0x800400F0 0x00000002 + + #============================================================================ + # DDR Controller Registers + #============================================================================ + # Manufacturer: Elpida + # Device Part Number: EDE1116AEBG + # Clock Freq.: 200MHz + # Density: 1Gb + # Chip Selects: 1 + # Number of Banks: 8 + # Row address: 13 + # Column address: 10 + #============================================================================ + mww 0x800E0000 0x00000000 + mww 0x800E0040 0x00000000 + mww 0x800E0054 0x00000000 + mww 0x800E0058 0x00000000 + mww 0x800E005C 0x00000000 + mww 0x800E0060 0x00000000 + mww 0x800E0064 0x00000000 + mww 0x800E0068 0x00010101 + mww 0x800E006C 0x01010101 + mww 0x800E0070 0x000f0f01 + mww 0x800E0074 0x0102020A + mww 0x800E007C 0x00010101 + mww 0x800E0080 0x00000100 + mww 0x800E0084 0x00000100 + mww 0x800E0088 0x00000000 + mww 0x800E008C 0x00000002 + mww 0x800E0090 0x01010000 + mww 0x800E0094 0x07080403 + mww 0x800E0098 0x06005003 + mww 0x800E009C 0x0A0000C8 + mww 0x800E00A0 0x02009C40 + mww 0x800E00A4 0x0002030C + mww 0x800E00A8 0x0036B009 + mww 0x800E00AC 0x031A0612 + mww 0x800E00B0 0x02030202 + mww 0x800E00B4 0x00C8001C + mww 0x800E00C0 0x00011900 + mww 0x800E00C4 0xffff0303 + mww 0x800E00C8 0x00012100 + mww 0x800E00CC 0xffff0303 + mww 0x800E00D0 0x00012100 + mww 0x800E00D4 0xffff0303 + mww 0x800E00D8 0x00012100 + mww 0x800E00DC 0xffff0303 + mww 0x800E00E0 0x00000003 + mww 0x800E00E8 0x00000000 + mww 0x800E0108 0x00000612 + mww 0x800E010C 0x01000f02 + mww 0x800E0114 0x00000200 + mww 0x800E0118 0x00020007 + mww 0x800E011C 0xf4004a27 + mww 0x800E0120 0xf4004a27 + mww 0x800E012C 0x07400300 + mww 0x800E0130 0x07400300 + mww 0x800E013C 0x00000005 + mww 0x800E0140 0x00000000 + mww 0x800E0144 0x00000000 + mww 0x800E0148 0x01000000 + mww 0x800E014C 0x01020408 + mww 0x800E0150 0x08040201 + mww 0x800E0154 0x000f1133 + mww 0x800E015C 0x00001f04 + mww 0x800E0160 0x00001f04 + mww 0x800E016C 0x00001f04 + mww 0x800E0170 0x00001f04 + mww 0x800E0288 0x00010000 + mww 0x800E028C 0x00030404 + mww 0x800E0290 0x00000003 + mww 0x800E02AC 0x01010000 + mww 0x800E02B0 0x01000000 + mww 0x800E02B4 0x03030000 + mww 0x800E02B8 0x00010303 + mww 0x800E02BC 0x01020202 + mww 0x800E02C0 0x00000000 + mww 0x800E02C4 0x02030303 + mww 0x800E02C8 0x21002103 + mww 0x800E02CC 0x00061200 + mww 0x800E02D0 0x06120612 + mww 0x800E02D4 0x04420442 + # Mode register 0 for CS1 and CS0, ok to program CS1 even if not used + mww 0x800E02D8 0x00000000 + # Mode register 0 for CS2 and CS3, not supported in this processor + mww 0x800E02DC 0x00040004 + # Mode register 1 for CS1 and CS0, ok to program CS1 even if not used + mww 0x800E02E0 0x00000000 + # Mode register 1 for CS2 and CS3, not supported in this processor + mww 0x800E02E4 0x00000000 + # Mode register 2 for CS1 and CS0, ok to program CS1 even if not used + mww 0x800E02E8 0x00000000 + # Mode register 2 for CS2 and CS3, not supported in this processor + mww 0x800E02EC 0x00000000 + # Mode register 3 for CS1 and CS0, ok to program CS1 even if not used + mww 0x800E02F0 0x00000000 + # Mode register 3 for CS2 and CS3, not supported in this processor + mww 0x800E02F4 0xffffffff + + #** start controller **# + mww 0x800E0040 0x00000001 + # bit[0]: start +} diff --git a/tcl/target/imx28.cfg b/tcl/target/imx28.cfg new file mode 100644 index 000000000..0cbedce40 --- /dev/null +++ b/tcl/target/imx28.cfg @@ -0,0 +1,38 @@ +# i.MX28 config file. +# based off of the imx21.cfg file. + +reset_config trst_and_srst + +#jtag nTRST and nSRST delay +adapter_nsrst_delay 100 +jtag_ntrst_delay 100 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx28 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + + +# Note above there is 1 tap + +# The CPU tap +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x079264f3 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + +# Create the GDB Target. +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs + +arm7_9 dcc_downloads enable