stm32x: add support for STM32F20x
ready for wider testing and comments on basic erase + programming. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>__archive__
Øyvind Harboe
parent
75cdbff5aa
commit
5ca7cbe2d2
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@ -0,0 +1,63 @@
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/***************************************************************************
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* Copyright (C) 2010 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2011 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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// Build : arm-eabi-gcc -c stm32f2xxx.S
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.text
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.syntax unified
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.cpu cortex-m3
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.thumb
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.thumb_func
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.global write
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/*
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r0 - source address
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r1 - target address
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r2 - count (halfword-16bit)
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r3 - result out
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r4 - flash base
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*/
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#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x0c /* offset of CR register in FLASH struct */
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write:
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write_half_word:
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ldr r3, STM32_PROG16
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str r3, [r4, #STM32_FLASH_CR_OFFSET]
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ldrh r3, [r0], #0x02 /* read one half-word from src, increment ptr */
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strh r3, [r1], #0x02 /* write one half-word from src, increment ptr */
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busy:
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ldr r3, [r4, #STM32_FLASH_SR_OFFSET]
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tst r3, #0x10000 /* BSY (bit0) == 1 => operation in progress */
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beq busy /* wait more... */
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tst r3, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
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bne exit /* fail... */
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subs r2, r2, #0x01 /* decrement counter */
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bne write_half_word /* write next half-word if anything left */
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exit:
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bkpt #0x00
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STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/
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@ -25,6 +25,7 @@ NOR_DRIVERS = \
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stmsmi.c \
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stellaris.c \
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stm32x.c \
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stm32f2xxx.c \
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str7x.c \
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str9x.c \
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str9xpec.c \
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@ -33,6 +33,7 @@ extern struct flash_driver aduc702x_flash;
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extern struct flash_driver stellaris_flash;
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extern struct flash_driver str9xpec_flash;
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extern struct flash_driver stm32x_flash;
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extern struct flash_driver stm32xf2xxx_flash;
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extern struct flash_driver tms470_flash;
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extern struct flash_driver ecosflash_flash;
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extern struct flash_driver ocl_flash;
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@ -60,6 +61,7 @@ static struct flash_driver *flash_drivers[] = {
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&stellaris_flash,
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&str9xpec_flash,
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&stm32x_flash,
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&stm32xf2xxx_flash,
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&tms470_flash,
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&ecosflash_flash,
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&ocl_flash,
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@ -0,0 +1,712 @@
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2011 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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#include <target/armv7m.h>
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/* Regarding performance:
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*
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* Short story - it might be best to leave the performance at
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* current levels.
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*
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* You may see a jump in speed if you change to using
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* 32bit words for the block programming.
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*
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* Its a shame you cannot use the double word as its
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* even faster - but you require external VPP for that mode.
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*
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* Having said all that 16bit writes give us the widest vdd
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* operating range, so may be worth adding a note to that effect.
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*
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*/
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/* Danger!!!! The STM32F1xxxx and STM32F2xxxx series actually have
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* quite different flash controllers.
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*
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* What's more scary is that the names of the registers and their
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* addresses are the same, but the actual bits and what they do are
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* can be very different.
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*
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* To reduce testing complexity and dangers of regressions,
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* a seperate file is used for stm32fx2222.
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*
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* 1mByte part with 4 x 16, 1 x 64, 7 x 128kBytes sectors
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*
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* What's the protection page size???
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*
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* Tested with STM3220F-EVAL board.
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*
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* STM32F21xx series for reference.
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*
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* RM0033
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* http://www.st.com/internet/mcu/product/250192.jsp
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*
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* PM0059
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* www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/CD00233952.pdf
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*
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* STM32F1xxx series - notice that this code was copy, pasted and knocked
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* into a stm32f2xxx driver, so in case something has been converted or
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* bugs haven't been fixed, here are the original manuals:
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*
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* RM0008 - Reference manual
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*
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* RM0042, the Flash programming manual for low-, medium- high-density and
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* connectivity line STM32F10xxx devices
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*
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* PM0068, the Flash programming manual for XL-density STM32F10xxx devices.
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*
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*/
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// Erase time can be as high as 1000ms, 10x this and it's toast...
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#define FLASH_ERASE_TIMEOUT 10000
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#define FLASH_WRITE_TIMEOUT 5
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#define STM32_FLASH_BASE 0x40023c00
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#define STM32_FLASH_ACR 0x40023c00
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#define STM32_FLASH_KEYR 0x40023c04
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#define STM32_FLASH_OPTKEYR 0x40023c08
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#define STM32_FLASH_SR 0x40023c0C
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#define STM32_FLASH_CR 0x40023c10
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#define STM32_FLASH_OPTCR 0x40023c14
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#define STM32_FLASH_OBR 0x40023c1C
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/* option byte location */
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#define STM32_OB_RDP 0x1FFFF800
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#define STM32_OB_USER 0x1FFFF802
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#define STM32_OB_DATA0 0x1FFFF804
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#define STM32_OB_DATA1 0x1FFFF806
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#define STM32_OB_WRP0 0x1FFFF808
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#define STM32_OB_WRP1 0x1FFFF80A
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#define STM32_OB_WRP2 0x1FFFF80C
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#define STM32_OB_WRP3 0x1FFFF80E
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/* FLASH_CR register bits */
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#define FLASH_PG (1 << 0)
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#define FLASH_SER (1 << 1)
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#define FLASH_MER (1 << 2)
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#define FLASH_STRT (1 << 16)
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#define FLASH_PSIZE_8 (0 << 8)
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#define FLASH_PSIZE_16 (1 << 8)
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#define FLASH_PSIZE_32 (2 << 8)
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#define FLASH_PSIZE_64 (3 << 8)
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#define FLASH_SNB(a) ((a) << 3)
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#define FLASH_LOCK (1 << 31)
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/* FLASH_SR register bits */
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#define FLASH_BSY (1 << 16)
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#define FLASH_PGSERR (1 << 7) // Programming sequence error
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#define FLASH_PGPERR (1 << 6) // Programming parallelism error
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#define FLASH_PGAERR (1 << 5) // Programming alignment error
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#define FLASH_WRPERR (1 << 4) // Write protection error
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#define FLASH_OPERR (1 << 1) // Operation error
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#define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR| FLASH_WRPERR| FLASH_OPERR)
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/* STM32_FLASH_OBR bit definitions (reading) */
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#define OPT_ERROR 0
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#define OPT_READOUT 1
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#define OPT_RDWDGSW 2
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#define OPT_RDRSTSTOP 3
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#define OPT_RDRSTSTDBY 4
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#define OPT_BFB2 5 /* dual flash bank only */
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/* register unlock keys */
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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struct stm32x_flash_bank
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{
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struct working_area *write_algorithm;
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int probed;
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};
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/* flash bank stm32x <base> <size> 0 0 <target#>
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*/
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FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
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{
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struct stm32x_flash_bank *stm32x_info;
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if (CMD_ARGC < 6)
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{
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LOG_WARNING("incomplete flash_bank stm32x configuration");
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return ERROR_FLASH_BANK_INVALID;
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}
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stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
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bank->driver_priv = stm32x_info;
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stm32x_info->write_algorithm = NULL;
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stm32x_info->probed = 0;
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return ERROR_OK;
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}
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static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
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{
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return reg;
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}
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static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
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{
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struct target *target = bank->target;
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return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
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}
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static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
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{
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struct target *target = bank->target;
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uint32_t status;
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int retval = ERROR_OK;
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/* wait for busy to clear */
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for (;;)
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{
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retval = stm32x_get_flash_status(bank, &status);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("status: 0x%" PRIx32 "", status);
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if ((status & FLASH_BSY) == 0)
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break;
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if (timeout-- <= 0)
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{
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LOG_ERROR("timed out waiting for flash");
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return ERROR_FAIL;
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}
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alive_sleep(1);
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}
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if (status & FLASH_WRPERR)
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{
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LOG_ERROR("stm32x device protected");
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retval = ERROR_FAIL;
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}
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/* Clear but report errors */
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if (status & FLASH_ERROR)
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{
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/* If this operation fails, we ignore it and report the original
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* retval
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*/
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target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
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status & FLASH_ERROR);
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}
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return retval;
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}
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static int stm32x_unlock_reg(struct target *target)
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{
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/* unlock flash registers */
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int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int stm32x_protect_check(struct flash_bank *bank)
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{
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return ERROR_OK;
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}
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static int stm32x_erase(struct flash_bank *bank, int first, int last)
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{
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struct target *target = bank->target;
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int i;
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if (bank->target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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int retval;
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retval = stm32x_unlock_reg(target);
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if (retval != ERROR_OK)
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return retval;
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/*
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Sector Erase
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To erase a sector, follow the procedure below:
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1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
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FLASH_SR register
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2. Set the SER bit and select the sector (out of the 12 sectors in the main memory block)
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you wish to erase (SNB) in the FLASH_CR register
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3. Set the STRT bit in the FLASH_CR register
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4. Wait for the BSY bit to be cleared
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*/
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for (i = first; i <= last; i++)
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{
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retval = target_write_u32(target,
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stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(i) | FLASH_STRT);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
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if (retval != ERROR_OK)
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return retval;
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bank->sectors[i].is_erased = 1;
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}
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retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
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{
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return ERROR_OK;
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}
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static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t buffer_size = 16384;
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struct working_area *source;
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uint32_t address = bank->base + offset;
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struct reg_param reg_params[5];
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struct armv7m_algorithm armv7m_info;
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int retval = ERROR_OK;
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/* see contib/loaders/flash/stm32x.s for src */
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static const uint16_t stm32x_flash_write_code_16[] = {
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// 00000000 <write>:
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0x4b07, // ldr r3, [pc, #28] (20 <STM32_PROG16>)
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0x6123, // str r3, [r4, #16]
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0xf830, 0x3b02, //ldrh.w r3, [r0], #2
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0xf821, 0x3b02, //strh.w r3, [r1], #2
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//0000000c <busy>:
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0x68e3, //ldr r3, [r4, #12]
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0xf413, 0x3f80, // tst.w r3, #65536 ; 0x10000
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0xd0fb, //beq.n c <busy>
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0xf013, 0x0ff0, //tst.w r3, #240 ; 0xf0
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0xd101, //bne.n 1e <exit>
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0x3a01, //subs r2, #1
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0xd1f0, //bne.n 0 <write>
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//0000001e <exit>:
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0xbe00, // bkpt 0x0000
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//00000020 <STM32_PROG16>:
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0x0101, 0x0000, // .word 0x00000101
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};
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// Flip endian
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uint8_t stm32x_flash_write_code[sizeof(stm32x_flash_write_code_16)*2];
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for (unsigned i = 0; i < sizeof(stm32x_flash_write_code_16) / 2; i++)
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{
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stm32x_flash_write_code[i*2 + 0] = stm32x_flash_write_code_16[i] & 0xff;
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stm32x_flash_write_code[i*2 + 1] = (stm32x_flash_write_code_16[i] >> 8) & 0xff;
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}
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if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
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&stm32x_info->write_algorithm) != ERROR_OK)
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{
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LOG_WARNING("no working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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};
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if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
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sizeof(stm32x_flash_write_code),
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(uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
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return retval;
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/* memory buffer */
|
||||
while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
|
||||
{
|
||||
buffer_size /= 2;
|
||||
if (buffer_size <= 256)
|
||||
{
|
||||
/* if we already allocated the writing code, but failed to get a
|
||||
* buffer, free the algorithm */
|
||||
if (stm32x_info->write_algorithm)
|
||||
target_free_working_area(target, stm32x_info->write_algorithm);
|
||||
|
||||
LOG_WARNING("no large enough working area available, can't do block memory writes");
|
||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||
}
|
||||
};
|
||||
|
||||
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
|
||||
armv7m_info.core_mode = ARMV7M_MODE_ANY;
|
||||
|
||||
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
|
||||
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
||||
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
|
||||
init_reg_param(®_params[3], "r3", 32, PARAM_IN_OUT);
|
||||
init_reg_param(®_params[4], "r4", 32, PARAM_OUT);
|
||||
|
||||
while (count > 0)
|
||||
{
|
||||
uint32_t thisrun_count = (count > (buffer_size / 2)) ?
|
||||
(buffer_size / 2) : count;
|
||||
|
||||
if ((retval = target_write_buffer(target, source->address,
|
||||
thisrun_count * 2, buffer)) != ERROR_OK)
|
||||
break;
|
||||
|
||||
buf_set_u32(reg_params[0].value, 0, 32, source->address);
|
||||
buf_set_u32(reg_params[1].value, 0, 32, address);
|
||||
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
|
||||
// R3 is a return value only
|
||||
buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
|
||||
|
||||
if ((retval = target_run_algorithm(target, 0, NULL,
|
||||
sizeof(reg_params) / sizeof(*reg_params),
|
||||
reg_params,
|
||||
stm32x_info->write_algorithm->address,
|
||||
0,
|
||||
10000, &armv7m_info)) != ERROR_OK)
|
||||
{
|
||||
LOG_ERROR("error executing stm32x flash write algorithm");
|
||||
break;
|
||||
}
|
||||
|
||||
uint32_t error = buf_get_u32(reg_params[3].value, 0, 32) & FLASH_ERROR;
|
||||
|
||||
if (error & FLASH_WRPERR)
|
||||
{
|
||||
LOG_ERROR("flash memory write protected");
|
||||
}
|
||||
|
||||
if (error != 0)
|
||||
{
|
||||
LOG_ERROR("flash write failed = %08x", error);
|
||||
/* Clear but report errors */
|
||||
target_write_u32(target, STM32_FLASH_SR, error);
|
||||
retval = ERROR_FAIL;
|
||||
break;
|
||||
}
|
||||
|
||||
buffer += thisrun_count * 2;
|
||||
address += thisrun_count * 2;
|
||||
count -= thisrun_count;
|
||||
}
|
||||
|
||||
target_free_working_area(target, source);
|
||||
target_free_working_area(target, stm32x_info->write_algorithm);
|
||||
|
||||
destroy_reg_param(®_params[0]);
|
||||
destroy_reg_param(®_params[1]);
|
||||
destroy_reg_param(®_params[2]);
|
||||
destroy_reg_param(®_params[3]);
|
||||
destroy_reg_param(®_params[4]);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
|
||||
uint32_t offset, uint32_t count)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
uint32_t words_remaining = (count / 2);
|
||||
uint32_t bytes_remaining = (count & 0x00000001);
|
||||
uint32_t address = bank->base + offset;
|
||||
uint32_t bytes_written = 0;
|
||||
int retval;
|
||||
|
||||
if (bank->target->state != TARGET_HALTED)
|
||||
{
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
if (offset & 0x1)
|
||||
{
|
||||
LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
|
||||
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
|
||||
}
|
||||
|
||||
retval = stm32x_unlock_reg(target);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* multiple half words (2-byte) to be programmed? */
|
||||
if (words_remaining > 0)
|
||||
{
|
||||
/* try using a block write */
|
||||
if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
|
||||
{
|
||||
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
|
||||
{
|
||||
/* if block write failed (no sufficient working area),
|
||||
* we use normal (slow) single dword accesses */
|
||||
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
buffer += words_remaining * 2;
|
||||
address += words_remaining * 2;
|
||||
words_remaining = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
|
||||
return retval;
|
||||
|
||||
/*
|
||||
Standard programming
|
||||
The Flash memory programming sequence is as follows:
|
||||
1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
|
||||
FLASH_SR register.
|
||||
2. Set the PG bit in the FLASH_CR register
|
||||
3. Perform the data write operation(s) to the desired memory address (inside main
|
||||
memory block or OTP area):
|
||||
– – Half-word access in case of x16 parallelism
|
||||
– Word access in case of x32 parallelism
|
||||
–
|
||||
4.
|
||||
Byte access in case of x8 parallelism
|
||||
Double word access in case of x64 parallelism
|
||||
Wait for the BSY bit to be cleared
|
||||
*/
|
||||
while (words_remaining > 0)
|
||||
{
|
||||
uint16_t value;
|
||||
memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
|
||||
|
||||
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
|
||||
FLASH_PG | FLASH_PSIZE_16);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = target_write_u16(target, address, value);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
bytes_written += 2;
|
||||
words_remaining--;
|
||||
address += 2;
|
||||
}
|
||||
|
||||
if (bytes_remaining)
|
||||
{
|
||||
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
|
||||
FLASH_PG | FLASH_PSIZE_8);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
retval = target_write_u8(target, address, buffer[bytes_written]);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
|
||||
return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
|
||||
}
|
||||
|
||||
static void setup_sector(struct flash_bank *bank, int start, int num, int size)
|
||||
{
|
||||
for (int i = start; i < (start + num) ; i++)
|
||||
{
|
||||
bank->sectors[i].offset = bank->size;
|
||||
bank->sectors[i].size = size;
|
||||
bank->size += bank->sectors[i].size;
|
||||
}
|
||||
}
|
||||
|
||||
static int stm32x_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
|
||||
int i;
|
||||
uint16_t num_pages;
|
||||
uint32_t device_id;
|
||||
uint32_t base_address = 0x08000000;
|
||||
|
||||
stm32x_info->probed = 0;
|
||||
|
||||
/* read stm32 device id register */
|
||||
int retval = target_read_u32(target, 0xE0042000, &device_id);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
|
||||
|
||||
/* get flash size from target. */
|
||||
retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
|
||||
if (retval != ERROR_OK)
|
||||
{
|
||||
LOG_WARNING("failed reading flash size, default to max target family");
|
||||
/* failed reading flash size, default to max target family */
|
||||
num_pages = 0xffff;
|
||||
}
|
||||
|
||||
if ((device_id & 0x7ff) != 0x411)
|
||||
{
|
||||
LOG_WARNING("Cannot identify target as a STM32 family, try the other STM32 drivers.");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
/* sectors sizes vary, handle this in a different code path
|
||||
* than the rest.
|
||||
*/
|
||||
// Uhhh.... what to use here?
|
||||
|
||||
/* calculate numbers of pages*/
|
||||
num_pages = 4 + 1 + 7;
|
||||
|
||||
if (bank->sectors)
|
||||
{
|
||||
free(bank->sectors);
|
||||
bank->sectors = NULL;
|
||||
}
|
||||
|
||||
bank->base = base_address;
|
||||
bank->num_sectors = num_pages;
|
||||
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
|
||||
|
||||
bank->size = 0;
|
||||
setup_sector(bank, 0, 4, 16 * 1024);
|
||||
setup_sector(bank, 4, 1, 64 * 1024);
|
||||
setup_sector(bank, 4+1, 7, 128 * 1024);
|
||||
|
||||
for (i = 0; i < num_pages; i++)
|
||||
{
|
||||
bank->sectors[i].is_erased = -1;
|
||||
bank->sectors[i].is_protected = 0;
|
||||
}
|
||||
|
||||
LOG_INFO("flash size = %dkBytes", bank->size / 1024);
|
||||
|
||||
stm32x_info->probed = 1;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int stm32x_auto_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
|
||||
if (stm32x_info->probed)
|
||||
return ERROR_OK;
|
||||
return stm32x_probe(bank);
|
||||
}
|
||||
|
||||
static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
uint32_t device_id;
|
||||
int printed;
|
||||
|
||||
/* read stm32 device id register */
|
||||
int retval = target_read_u32(target, 0xE0042000, &device_id);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
if ((device_id & 0x7ff) == 0x411)
|
||||
{
|
||||
printed = snprintf(buf, buf_size, "stm32x (1mByte part) - Rev: ");
|
||||
buf += printed;
|
||||
buf_size -= printed;
|
||||
|
||||
switch (device_id >> 16)
|
||||
{
|
||||
case 0x1000:
|
||||
snprintf(buf, buf_size, "A");
|
||||
break;
|
||||
|
||||
case 0x2000:
|
||||
snprintf(buf, buf_size, "B");
|
||||
break;
|
||||
|
||||
case 0x1001:
|
||||
snprintf(buf, buf_size, "Z");
|
||||
break;
|
||||
|
||||
default:
|
||||
snprintf(buf, buf_size, "unknown");
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static const struct command_registration stm32x_exec_command_handlers[] = {
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
static const struct command_registration stm32x_command_handlers[] = {
|
||||
{
|
||||
.name = "stm32f2xxx",
|
||||
.mode = COMMAND_ANY,
|
||||
.help = "stm32f2xxx flash command group",
|
||||
.chain = stm32x_exec_command_handlers,
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
struct flash_driver stm32xf2xxx_flash = {
|
||||
.name = "stm32f2xxx",
|
||||
.commands = stm32x_command_handlers,
|
||||
.flash_bank_command = stm32x_flash_bank_command,
|
||||
.erase = stm32x_erase,
|
||||
.protect = stm32x_protect,
|
||||
.write = stm32x_write,
|
||||
.read = default_flash_read,
|
||||
.probe = stm32x_probe,
|
||||
.auto_probe = stm32x_auto_probe,
|
||||
.erase_check = default_flash_mem_blank_check,
|
||||
.protect_check = stm32x_protect_check,
|
||||
.info = get_stm32x_info,
|
||||
};
|
||||
Loading…
Reference in New Issue