flash/nor: flash driver for Synwit SWM050 MCUs
SWM050 is a series of MCU product by Foshan Synwit Tech, which is available in TSSOP-8 or SSOP-16 packages. Adds flash driver for the internal 8KiB flash of the MCU. The registers are based on reverse engineering the J-Flash blob provided by the vendor. Also adds a pre-made cfg file. Change-Id: I0b29f0c0d062883542ee743e0750a4c6b6609ebd Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Caleb Szalacinski <contact@skiboy.net> Reviewed-on: http://openocd.zylin.com/4927 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>bscan_optimization
Caleb Szalacinski
Tomas Vanek
parent
642a9310ca
commit
5a235226f0
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@ -7002,6 +7002,23 @@ unlock str9 device.
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@end deffn
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@deffn {Flash Driver} swm050
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@cindex swm050
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All members of the swm050 microcontroller family from Foshan Synwit Tech.
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@example
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flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
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@end example
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One swm050-specific command is defined:
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@deffn Command {swm050 mass_erase} bank_id
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Erases the entire flash bank.
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@end deffn
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@end deffn
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@deffn {Flash Driver} tms470
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Most members of the TMS470 microcontroller family from Texas Instruments
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include internal flash and use ARM7TDMI cores.
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@ -63,6 +63,7 @@ NOR_DRIVERS = \
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%D%/str7x.c \
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%D%/str9x.c \
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%D%/str9xpec.c \
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%D%/swm050.c \
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%D%/tms470.c \
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%D%/virtual.c \
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%D%/w600.c \
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@ -77,6 +77,7 @@ extern const struct flash_driver stmsmi_flash;
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extern const struct flash_driver str7x_flash;
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extern const struct flash_driver str9x_flash;
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extern const struct flash_driver str9xpec_flash;
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extern const struct flash_driver swm050_flash;
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extern const struct flash_driver tms470_flash;
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extern const struct flash_driver virtual_flash;
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extern const struct flash_driver w600_flash;
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@ -146,6 +147,7 @@ static const struct flash_driver * const flash_drivers[] = {
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&str7x_flash,
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&str9x_flash,
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&str9xpec_flash,
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&swm050_flash,
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&tms470_flash,
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&virtual_flash,
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&xcf_flash,
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@ -0,0 +1,211 @@
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/***************************************************************************
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* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> *
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* Copyright (C) 2019 Caleb Szalacinski <contact@skiboy.net> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include <target/image.h>
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#define SWM050_DELAY 100
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#define SWM050_FLASH_PAGE_SIZE 0x200
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#define SWM050_FLASH_PAGES 16
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#define SWM050_CPU_ID 0xE000ED00
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#define SWM050_CPU_ID_VAL 0x410CC200
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#define SWM050_FLASH_REG1 0x1F000000
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#define SWM050_FLASH_REG2 0x1F000038
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#define SWM050_FLASH_KEY 0xAAAAAAAA
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#define SWM050_SYSCTL_CFG_0 0x400F0000
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#define SWM050_SYSCTL_DBLF 0x400F0008
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static int swm050_erase(struct flash_bank *bank, int first, int last)
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{
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struct target *target = bank->target;
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int retval, curr_page;
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uint32_t curr_addr;
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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/* Perform erase */
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retval = target_write_u32(target, SWM050_FLASH_REG1, 0x4);
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if (retval != ERROR_OK)
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return retval;
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for (curr_page = first; curr_page <= last; curr_page++) {
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curr_addr = bank->base + (SWM050_FLASH_PAGE_SIZE * curr_page);
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/* Perform write */
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retval = target_write_u32(target, curr_addr, SWM050_FLASH_KEY);
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if (retval != ERROR_OK)
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return retval;
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alive_sleep(SWM050_DELAY);
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}
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/* Close flash interface */
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retval = target_write_u32(target, SWM050_FLASH_REG1, 0x0);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int swm050_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
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{
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struct target *target = bank->target;
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int retval;
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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retval = ERROR_TARGET_NOT_HALTED;
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return retval;
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}
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/* Perform write */
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retval = target_write_u32(target, SWM050_FLASH_REG1, 0x1);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_memory(target, bank->base + offset, 4, count/4, buffer);
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if (retval != ERROR_OK)
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return retval;
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/* Close flash interface */
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retval = target_write_u32(target, SWM050_FLASH_REG1, 0x0);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int swm050_probe(struct flash_bank *bank)
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{
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return ERROR_OK;
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}
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static int swm050_mass_erase(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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int retval;
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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/* Perform mass erase */
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retval = target_write_u32(target, SWM050_FLASH_REG1, 0x6);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, SWM050_FLASH_REG2, 0x1);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, 0x0, SWM050_FLASH_KEY);
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if (retval != ERROR_OK)
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return retval;
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alive_sleep(SWM050_DELAY);
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/* Close flash interface */
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retval = target_write_u32(target, SWM050_FLASH_REG1, 0x0);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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COMMAND_HANDLER(swm050_handle_mass_erase_command)
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{
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if (CMD_ARGC < 1)
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return ERROR_COMMAND_SYNTAX_ERROR;
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struct flash_bank *bank;
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int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
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if (ERROR_OK != retval)
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return retval;
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retval = swm050_mass_erase(bank);
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if (retval == ERROR_OK)
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command_print(CMD, "swm050 mass erase complete");
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else
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command_print(CMD, "swm050 mass erase failed");
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return retval;
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}
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FLASH_BANK_COMMAND_HANDLER(swm050_flash_bank_command)
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{
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if (bank->sectors) {
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free(bank->sectors);
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bank->sectors = NULL;
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}
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bank->write_start_alignment = 4;
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bank->write_end_alignment = 4;
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bank->size = SWM050_FLASH_PAGE_SIZE * SWM050_FLASH_PAGES;
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bank->num_sectors = SWM050_FLASH_PAGES;
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bank->sectors = alloc_block_array(0, SWM050_FLASH_PAGE_SIZE, SWM050_FLASH_PAGES);
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if (!bank->sectors)
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return ERROR_FAIL;
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for (int i = 0; i < bank->num_sectors; i++)
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bank->sectors[i].is_protected = 0;
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return ERROR_OK;
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}
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static const struct command_registration swm050_exec_command_handlers[] = {
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{
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.name = "mass_erase",
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.handler = swm050_handle_mass_erase_command,
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.mode = COMMAND_EXEC,
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.usage = "bank_id",
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.help = "Erase entire flash device.",
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},
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COMMAND_REGISTRATION_DONE
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};
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static const struct command_registration swm050_command_handlers[] = {
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{
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.name = "swm050",
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.mode = COMMAND_ANY,
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.help = "swm050 flash command group",
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.usage = "",
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.chain = swm050_exec_command_handlers,
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},
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COMMAND_REGISTRATION_DONE
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};
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struct flash_driver swm050_flash = {
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.name = "swm050",
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.commands = swm050_command_handlers,
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.flash_bank_command = swm050_flash_bank_command,
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.erase = swm050_erase,
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.write = swm050_write,
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.read = default_flash_read,
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.probe = swm050_probe,
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.auto_probe = swm050_probe,
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.erase_check = default_flash_blank_check,
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.free_driver_priv = default_flash_free_driver_priv,
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};
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@ -0,0 +1,45 @@
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# Synwit SWM050
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME swm050
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}
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set _CHIPSERIES swm050
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x400
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x410CC200
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}
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swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
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$_TARGETNAME configure -event reset-init {
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# Stop the watchdog, just to be safe
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mww 0x40019000 0x00
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# Set clock divider value to 1
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mww 0x400F0000 0x01
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# Set system clock to 18Mhz
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mww 0x400F0008 0x00
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}
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# SWM050 (Cortex-M0 core) supports SYSRESETREQ
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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