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LPC1768.cfg -- partial fixes for bogus reset-init handler 

Cortex-M targets don't support ARM instructions.

Leave the NVIC.VTOR setup alone, but comment how the whole
routine looks like one big bug...

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
__archive__
David Brownell 2010-02-15 13:39:16 -08:00
parent 52d4ba3467
commit 5869992314
1 changed files with 4 additions and 4 deletions
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8
tcl/target/lpc1768.cfg
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@ -33,11 +33,11 @@ target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNA
# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM) # LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
# REVISIT is there any good reason to have this reset-init event handler??
# Normally they should set up (board-specific) clocking then probe the flash...
$_TARGETNAME configure -event reset-init { $_TARGETNAME configure -event reset-init {
# Force target into ARM state # Force NVIC.VTOR to point to flash at 0 ...
arm core_state arm # WHY? This is it's reset value; we run right after reset!!
#do not remap 0x0000-0x0020 to anything but the flash
# mwb 0xE01FC040 0x01
mwb 0xE000ED08 0x00 mwb 0xE000ED08 0x00
} }