- Support for AT91SAM7xx512 chips
git-svn-id: svn://svn.berlios.de/openocd/trunk@201 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
mlu
parent
7658f61ce7
commit
580bb85201
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@ -61,9 +61,10 @@ int at91sam7_erase_check(struct flash_bank_s *bank);
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int at91sam7_protect_check(struct flash_bank_s *bank);
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int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
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u32 at91sam7_get_flash_status(flash_bank_t *bank);
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void at91sam7_set_flash_mode(flash_bank_t *bank,int mode);
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u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
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u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane);
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void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);
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u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout);
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int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen);
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int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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flash_driver_t at91sam7_flash =
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@ -80,6 +81,9 @@ flash_driver_t at91sam7_flash =
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.info = at91sam7_info
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};
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u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
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u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
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u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
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char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
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long NVPSIZ[16] = {
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@ -129,12 +133,12 @@ int at91sam7_register_commands(struct command_context_s *cmd_ctx)
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return ERROR_OK;
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}
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u32 at91sam7_get_flash_status(flash_bank_t *bank)
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u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane)
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{
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target_t *target = bank->target;
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u32 fsr;
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target_read_u32(target, MC_FSR, &fsr);
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target_read_u32(target, MC_FSR[flashplane], &fsr);
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return fsr;
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}
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@ -146,6 +150,7 @@ void at91sam7_read_clock_info(flash_bank_t *bank)
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target_t *target = bank->target;
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u32 mckr, mcfr, pllr;
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unsigned long tmp = 0, mainfreq;
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int flashplane;
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/* Read main clock freqency register */
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target_read_u32(target, CKGR_MCFR, &mcfr);
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@ -155,10 +160,12 @@ void at91sam7_read_clock_info(flash_bank_t *bank)
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target_read_u32(target, CKGR_PLLR, &pllr);
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at91sam7_info->mck_valid = 0;
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switch (mckr & PMC_MCKR_CSS) {
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switch (mckr & PMC_MCKR_CSS)
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{
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case 0: /* Slow Clock */
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at91sam7_info->mck_valid = 1;
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tmp = RC_FREQ;
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mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
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tmp = mainfreq;
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break;
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case 1: /* Main Clock */
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if (mcfr & CKGR_MCFR_MAINRDY)
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@ -194,17 +201,20 @@ void at91sam7_read_clock_info(flash_bank_t *bank)
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at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
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/* Forget old flash timing */
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at91sam7_set_flash_mode(bank,FMR_TIMING_NONE);
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for (flashplane = 0; flashplane<at91sam7_info->num_planes; flashplane++)
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{
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at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NONE);
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}
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}
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/* Setup the timimg registers for nvbits or normal flash */
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void at91sam7_set_flash_mode(flash_bank_t *bank,int mode)
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void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)
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{
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u32 fmr, fmcn = 0, fws = 0;
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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target_t *target = bank->target;
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if (mode && (mode != at91sam7_info->flashmode))
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if (mode && (mode != at91sam7_info->flashmode[flashplane]))
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{
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/* Always round up (ceil) */
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if (mode==FMR_TIMING_NVBITS)
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@ -231,25 +241,25 @@ void at91sam7_set_flash_mode(flash_bank_t *bank,int mode)
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if (at91sam7_info->mck_freq > 30000000ul)
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fws = 1;
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DEBUG("fmcn: %i", fmcn);
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DEBUG("fmcn[%i]: %i", flashplane, fmcn);
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fmr = fmcn << 16 | fws << 8;
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target_write_u32(target, MC_FMR, fmr);
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target_write_u32(target, MC_FMR[flashplane], fmr);
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}
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at91sam7_info->flashmode = mode;
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at91sam7_info->flashmode[flashplane] = mode;
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}
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u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
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u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout)
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{
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u32 status;
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while ((!((status = at91sam7_get_flash_status(bank)) & waitbits)) && (timeout-- > 0))
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while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0))
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{
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DEBUG("status: 0x%x", status);
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DEBUG("status[%i]: 0x%x", flashplane, status);
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usleep(1000);
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}
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DEBUG("status: 0x%x", status);
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DEBUG("status[%i]: 0x%x", flashplane, status);
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if (status & 0x0C)
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{
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@ -267,27 +277,27 @@ u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
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/* Send one command to the AT91SAM flash controller */
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int at91sam7_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
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int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen)
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{
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u32 fcr;
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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target_t *target = bank->target;
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fcr = (0x5A<<24) | (pagen<<8) | cmd;
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target_write_u32(target, MC_FCR, fcr);
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DEBUG("Flash command: 0x%x, pagenumber:%u", fcr, pagen);
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fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd;
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target_write_u32(target, MC_FCR[flashplane], fcr);
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DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen);
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if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
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{
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/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
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if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
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if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_EOL, 10)&0x0C)
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{
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return ERROR_FLASH_OPERATION_FAILED;
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}
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return ERROR_OK;
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}
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if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
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if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_FRDY, 10)&0x0C)
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{
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return ERROR_FLASH_OPERATION_FAILED;
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}
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@ -300,6 +310,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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target_t *target = bank->target;
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u32 cidr, status;
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int sectornum;
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if (bank->target->state != TARGET_HALTED)
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{
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@ -327,22 +338,40 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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bank->size = NVPSIZ[at91sam7_info->cidr_nvpsiz];
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at91sam7_info->target_name = "Unknown";
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/* Support just for bulk erase of the whole device */
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/* Support just for bulk erase of a single flash plane, whole device if flash size <= 256k */
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if (NVPSIZ[at91sam7_info->cidr_nvpsiz]<0x80000) /* Flash size less than 512K, one flash plane */
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{
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bank->num_sectors = 1;
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bank->sectors = malloc(sizeof(flash_sector_t));
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bank->sectors[0].offset = 0;
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bank->sectors[0].size = bank->size;
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bank->sectors[0].is_erased = -1;
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bank->sectors[0].is_protected = -1;
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}
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else /* Flash size 512K or larger, several flash planes */
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{
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bank->num_sectors = NVPSIZ[at91sam7_info->cidr_nvpsiz]/0x40000;
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bank->sectors = malloc(bank->num_sectors*sizeof(flash_sector_t));
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for (sectornum=0; sectornum<bank->num_sectors; sectornum++)
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{
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bank->sectors[sectornum].offset = sectornum*0x40000;
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bank->sectors[sectornum].size = 0x40000;
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bank->sectors[sectornum].is_erased = -1;
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bank->sectors[sectornum].is_protected = -1;
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}
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}
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DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );
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/* Read main and master clock freqency register */
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at91sam7_read_clock_info(bank);
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status = at91sam7_get_flash_status(bank);
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at91sam7_info->lockbits = status>>16;
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at91sam7_info->num_planes = 1;
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status = at91sam7_get_flash_status(bank, 0);
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at91sam7_info->securitybit = (status>>4)&0x01;
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at91sam7_protect_check(bank); /* TODO Check the protect check */
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if (at91sam7_info->cidr_arch == 0x70 )
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{
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@ -350,6 +379,17 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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at91sam7_info->nvmbits = (status>>8)&0x03;
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bank->base = 0x100000;
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bank->bus_width = 4;
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if (bank->size==0x80000) /* AT91SAM7S512 */
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{
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at91sam7_info->target_name = "AT91SAM7S512";
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at91sam7_info->num_planes = 2;
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if (at91sam7_info->num_planes != bank->num_sectors)
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WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
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at91sam7_info->num_lockbits = 2*16;
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at91sam7_info->pagesize = 256;
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at91sam7_info->pages_in_lockregion = 64;
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at91sam7_info->num_pages = 2*16*64;
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}
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if (bank->size==0x40000) /* AT91SAM7S256 */
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{
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at91sam7_info->target_name = "AT91SAM7S256";
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@ -392,6 +432,17 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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at91sam7_info->nvmbits = (status>>8)&0x07;
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bank->base = 0x100000;
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bank->bus_width = 4;
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if (bank->size==0x80000) /* AT91SAM7XC512 */
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{
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at91sam7_info->target_name = "AT91SAM7XC512";
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at91sam7_info->num_planes = 2;
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if (at91sam7_info->num_planes != bank->num_sectors)
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WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
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at91sam7_info->num_lockbits = 2*16;
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at91sam7_info->pagesize = 256;
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at91sam7_info->pages_in_lockregion = 64;
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at91sam7_info->num_pages = 2*16*64;
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}
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if (bank->size==0x40000) /* AT91SAM7XC256 */
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{
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at91sam7_info->target_name = "AT91SAM7XC256";
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@ -421,6 +472,9 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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if (bank->size==0x80000) /* AT91SAM7SE512 */
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{
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at91sam7_info->target_name = "AT91SAM7SE512";
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at91sam7_info->num_planes = 2;
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if (at91sam7_info->num_planes != bank->num_sectors)
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WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
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at91sam7_info->num_lockbits = 32;
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at91sam7_info->pagesize = 256;
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at91sam7_info->pages_in_lockregion = 64;
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@ -452,6 +506,18 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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at91sam7_info->nvmbits = (status>>8)&0x07;
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bank->base = 0x100000;
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bank->bus_width = 4;
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if (bank->size==0x80000) /* AT91SAM7X512 */
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{
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at91sam7_info->target_name = "AT91SAM7X512";
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at91sam7_info->num_planes = 2;
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if (at91sam7_info->num_planes != bank->num_sectors)
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WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
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at91sam7_info->num_lockbits = 32;
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at91sam7_info->pagesize = 256;
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at91sam7_info->pages_in_lockregion = 64;
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at91sam7_info->num_pages = 2*16*64;
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DEBUG("Support for AT91SAM7X512 is experimental in this version!");
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}
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if (bank->size==0x40000) /* AT91SAM7X256 */
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{
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at91sam7_info->target_name = "AT91SAM7X256";
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@ -512,6 +578,7 @@ int at91sam7_erase_check(struct flash_bank_s *bank)
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int at91sam7_protect_check(struct flash_bank_s *bank)
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{
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u32 status;
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int flashplane;
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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@ -526,8 +593,11 @@ int at91sam7_protect_check(struct flash_bank_s *bank)
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return ERROR_FLASH_OPERATION_FAILED;
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}
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status = at91sam7_get_flash_status(bank);
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at91sam7_info->lockbits = status >> 16;
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for (flashplane=0;flashplane<at91sam7_info->num_planes;flashplane++)
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{
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status = at91sam7_get_flash_status(bank, flashplane);
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at91sam7_info->lockbits[flashplane] = (status >> 16);
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}
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return ERROR_OK;
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}
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@ -537,6 +607,7 @@ int at91sam7_protect_check(struct flash_bank_s *bank)
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int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
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{
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at91sam7_flash_bank_t *at91sam7_info;
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int i;
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if (argc < 6)
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{
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@ -549,6 +620,8 @@ int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
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/* part wasn't probed for info yet */
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at91sam7_info->cidr = 0;
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for (i=0;i<4;i++)
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at91sam7_info->flashmode[i]=0;
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return ERROR_OK;
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}
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@ -556,6 +629,7 @@ int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
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int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
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{
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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u8 flashplane;
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if (bank->target->state != TARGET_HALTED)
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{
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@ -583,22 +657,25 @@ int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
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else return ERROR_FLASH_SECTOR_INVALID;
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}
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if ((first != 0) || (last != (bank->num_sectors-1)))
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{
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WARNING("Can only erase the whole flash area, pages are autoerased on write");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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/* Configure the flash controller timing */
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at91sam7_read_clock_info(bank);
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at91sam7_set_flash_mode(bank,FMR_TIMING_FLASH);
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for (flashplane = first; flashplane<=last; flashplane++)
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{
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/* Configure the flash controller timing */
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at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH);
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if (at91sam7_flash_command(bank, flashplane, EA, 0) != ERROR_OK)
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{
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return ERROR_FLASH_OPERATION_FAILED;
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}
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}
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return ERROR_OK;
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return at91sam7_flash_command(bank, EA, 0);
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}
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int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
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{
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u32 cmd, pagen, status;
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u8 flashplane;
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int lockregion;
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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@ -624,25 +701,27 @@ int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
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return ERROR_FLASH_OPERATION_FAILED;
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}
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/* Configure the flash controller timing */
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at91sam7_read_clock_info(bank);
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at91sam7_set_flash_mode(bank,FMR_TIMING_NVBITS);
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for (lockregion=first;lockregion<=last;lockregion++)
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{
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pagen = lockregion*at91sam7_info->pages_in_lockregion;
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flashplane = (pagen>>10)&0x03;
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/* Configure the flash controller timing */
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at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NVBITS);
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if (set)
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cmd = SLB;
|
||||
else
|
||||
cmd = CLB;
|
||||
if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
|
||||
|
||||
if (at91sam7_flash_command(bank, flashplane, cmd, pagen) != ERROR_OK)
|
||||
{
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
}
|
||||
|
||||
status = at91sam7_get_flash_status(bank);
|
||||
at91sam7_info->lockbits = status>>16;
|
||||
at91sam7_protect_check(bank);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -654,6 +733,7 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
|||
target_t *target = bank->target;
|
||||
u32 dst_min_alignment, wcount, bytes_remaining = count;
|
||||
u32 first_page, last_page, pagen, buffer_pos;
|
||||
u8 flashplane;
|
||||
|
||||
if (bank->target->state != TARGET_HALTED)
|
||||
{
|
||||
|
|
@ -690,11 +770,10 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
|||
|
||||
DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);
|
||||
|
||||
/* Configure the flash controller timing */
|
||||
at91sam7_read_clock_info(bank);
|
||||
at91sam7_set_flash_mode(bank,FMR_TIMING_FLASH);
|
||||
|
||||
for (pagen=first_page; pagen<last_page; pagen++) {
|
||||
for (pagen=first_page; pagen<last_page; pagen++)
|
||||
{
|
||||
if (bytes_remaining<dst_min_alignment)
|
||||
count = bytes_remaining;
|
||||
else
|
||||
|
|
@ -704,14 +783,17 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
|||
/* Write one block to the PageWriteBuffer */
|
||||
buffer_pos = (pagen-first_page)*dst_min_alignment;
|
||||
wcount = CEIL(count,4);
|
||||
target->type->write_memory(target, bank->base, 4, wcount, buffer+buffer_pos);
|
||||
target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos);
|
||||
flashplane = (pagen>>10)&0x3;
|
||||
|
||||
/* Configure the flash controller timing */
|
||||
at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH);
|
||||
/* Send Write Page command to Flash Controller */
|
||||
if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
|
||||
if (at91sam7_flash_command(bank, flashplane, WP, pagen) != ERROR_OK)
|
||||
{
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
DEBUG("Write page number:%i", pagen);
|
||||
DEBUG("Write flash plane:%i page number:%i", flashplane, pagen);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
|
|
@ -741,7 +823,7 @@ int at91sam7_probe(struct flash_bank_s *bank)
|
|||
|
||||
int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||
{
|
||||
int printed;
|
||||
int printed, flashplane;
|
||||
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
|
||||
|
||||
at91sam7_read_part_info(bank);
|
||||
|
|
@ -758,7 +840,8 @@ int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
|||
buf += printed;
|
||||
buf_size -= printed;
|
||||
|
||||
printed = snprintf(buf, buf_size, "cidr: 0x%8.8x, arch: 0x%4.4x, eproc: %s, version:0x%3.3x, flashsize: 0x%8.8x\n", at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc], at91sam7_info->cidr_version, bank->size);
|
||||
printed = snprintf(buf, buf_size, "cidr: 0x%8.8x, arch: 0x%4.4x, eproc: %s, version:0x%3.3x, flashsize: 0x%8.8x\n",
|
||||
at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc], at91sam7_info->cidr_version, bank->size);
|
||||
buf += printed;
|
||||
buf_size -= printed;
|
||||
|
||||
|
|
@ -766,8 +849,22 @@ int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
|||
buf += printed;
|
||||
buf_size -= printed;
|
||||
|
||||
if (at91sam7_info->num_planes>1) {
|
||||
printed = snprintf(buf, buf_size, "flashplanes: %i, pagesize: %i, lock regions: %i, pages in lock region: %i \n",
|
||||
at91sam7_info->num_planes, at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->num_pages/at91sam7_info->num_lockbits);
|
||||
buf += printed;
|
||||
buf_size -= printed;
|
||||
for (flashplane=0; flashplane<at91sam7_info->num_planes; flashplane++)
|
||||
{
|
||||
printed = snprintf(buf, buf_size, "lockbits[%i]: 0x%4.4x, ", flashplane, at91sam7_info->lockbits[flashplane]);
|
||||
buf += printed;
|
||||
buf_size -= printed;
|
||||
}
|
||||
}
|
||||
else
|
||||
if (at91sam7_info->num_lockbits>0) {
|
||||
printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->lockbits,at91sam7_info->num_pages/at91sam7_info->num_lockbits);
|
||||
printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n",
|
||||
at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->lockbits[0], at91sam7_info->num_pages/at91sam7_info->num_lockbits);
|
||||
buf += printed;
|
||||
buf_size -= printed;
|
||||
}
|
||||
|
|
@ -854,14 +951,14 @@ int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd,
|
|||
|
||||
/* Configure the flash controller timing */
|
||||
at91sam7_read_clock_info(bank);
|
||||
at91sam7_set_flash_mode(bank,FMR_TIMING_NVBITS);
|
||||
at91sam7_set_flash_mode(bank, 0, FMR_TIMING_NVBITS);
|
||||
|
||||
if (at91sam7_flash_command(bank, flashcmd, (u16)(bit)) != ERROR_OK)
|
||||
if (at91sam7_flash_command(bank, 0, flashcmd, (u16)(bit)) != ERROR_OK)
|
||||
{
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
status = at91sam7_get_flash_status(bank);
|
||||
status = at91sam7_get_flash_status(bank, 0);
|
||||
DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n",flashcmd,bit,status);
|
||||
at91sam7_info->nvmbits = (status>>8)&((1<<at91sam7_info->num_nvmbits)-1);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue