diff --git a/src/target/target/stm32.cfg b/src/target/target/stm32.cfg
new file mode 100644
index 000000000..68c42e5b5
--- /dev/null
+++ b/src/target/target/stm32.cfg
@@ -0,0 +1,23 @@
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+jtag_device 5 0x1 0x1 0x1e
+
+#target <type> <startup mode>
+#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
+target cortex_m3 little reset_halt 0
+run_and_halt_time 0 30
+
+working_area 0 0x20000000 16384 nobackup
+
+#flash bank str7x <base> <size> 0 0 <target#> <variant>
+flash bank stm32x 0x00000000 0x00000000 0 0 0
+
+# For more information about the configuration files, take a look at:
+# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger