David Brownell <david-b@pacbell.net>
lean up some loose ends with the ARM disassembler
- Add a header comment describing its current state and uses
and referencing the now-generally-available V7 arch spec
- Support some mode switch instructions:
* Thumb to Jazelle (BXJ)
* Thumb to ThumbEE (ENTERX)
* ThumbEE to Thumb (LEAVEX)
- Improve that recent warning fix (and associated whitespace goof)
- Declare the rest of the internal code and data "static". A
compiler may use this, and it helps clarify the scope of these
routines (e.g. what changes to them could affect).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
oharboe
parent
2c76cd7171
commit
57e12b7e45
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@ -28,20 +28,86 @@
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#include "log.h"
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/*
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* This disassembler supports two main functions for OpenOCD:
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*
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* - Various "disassemble" commands. OpenOCD can serve as a
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* machine-language debugger, without help from GDB.
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*
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* - Single stepping. Not all ARM cores support hardware single
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* stepping. To work without that support, the debugger must
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* be able to decode instructions to find out where to put a
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* "next instruction" breakpoint.
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*
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* In addition, interpretation of ETM trace data needs some of the
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* decoding mechanisms.
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*
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* At this writing (September 2009) neither function is complete.
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*
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* - ARM decoding
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* * Old-style syntax (not UAL) is generally used
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* * VFP instructions are not understood (ARMv5 and later)
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* except as coprocessor 10/11 operations
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* * Most ARM instructions through ARMv6 are decoded, but some
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* of the post-ARMv4 opcodes may not be handled yet
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* * NEON instructions are not understood (ARMv7-A)
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*
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* - Thumb/Thumb2 decoding
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* * UAL syntax should be consistently used
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* * Any Thumb2 instructions used in Cortex-M3 (ARMv7-M) should
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* be handled properly. Accordingly, so should the subset
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* used in Cortex-M0/M1; and "original" 16-bit Thumb from
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* ARMv4T and ARMv5T.
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* * Conditional effects of Thumb2 "IT" (if-then) instructions
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* are not handled: the affected instructions are not shown
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* with their now-conditional suffixes.
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* * Some ARMv6 and ARMv7-M Thumb2 instructions may not be
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* handled (minimally for coprocessor access).
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* * SIMD instructions, and some other Thumb2 instructions
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* from ARMv7-A, are not understood.
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*
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* - ThumbEE decoding
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* * As a Thumb2 variant, the Thumb2 comments (above) apply.
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* * Opcodes changed by ThumbEE mode are not handled; these
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* instructions wrongly decode as LDM and STM.
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*
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* - Jazelle decoding ... no support whatsoever for Jazelle mode
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* or decoding. ARM encourages use of the more generic ThumbEE
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* mode, instead of Jazelle mode, in current chips.
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*
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* - Single-step/emulation ... spotty support, which is only weakly
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* tested. Thumb2 is not supported. (Arguably a full simulator
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* is not needed to support just single stepping. Recognizing
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* branch vs non-branch instructions suffices, except when the
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* instruction faults and triggers a synchronous exception which
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* can be intercepted using other means.)
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*
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* ARM DDI 0406B "ARM Architecture Reference Manual, ARM v7-A and
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* ARM v7-R edition" gives the most complete coverage of the various
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* generations of ARM instructions. At this writing it is publicly
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* accessible to anyone willing to create an account at the ARM
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* web site; see http://www.arm.com/documentation/ for information.
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*
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* ARM DDI 0403C "ARMv7-M Architecture Reference Manual" provides
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* more details relevant to the Thumb2-only processors (such as
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* the Cortex-M implementations).
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*/
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/* textual represenation of the condition field */
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/* ALways (default) is ommitted (empty string) */
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char *arm_condition_strings[] =
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static const char *arm_condition_strings[] =
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{
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"EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "", "NV"
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};
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/* make up for C's missing ROR */
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uint32_t ror(uint32_t value, int places)
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static uint32_t ror(uint32_t value, int places)
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{
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return (value >> places) | (value << (32 - places));
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}
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int evaluate_pld(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_pld(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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/* PLD */
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if ((opcode & 0x0d70f0000) == 0x0550f000)
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@ -62,7 +128,8 @@ int evaluate_pld(uint32_t opcode, uint32_t address, arm_instruction_t *instructi
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return -1;
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}
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int evaluate_swi(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_swi(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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instruction->type = ARM_SWI;
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@ -73,7 +140,8 @@ int evaluate_swi(uint32_t opcode, uint32_t address, arm_instruction_t *instructi
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return ERROR_OK;
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}
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int evaluate_blx_imm(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_blx_imm(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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int offset;
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uint32_t immediate;
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@ -105,7 +173,8 @@ int evaluate_blx_imm(uint32_t opcode, uint32_t address, arm_instruction_t *instr
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return ERROR_OK;
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}
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int evaluate_b_bl(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_b_bl(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t L;
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uint32_t immediate;
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@ -142,7 +211,8 @@ int evaluate_b_bl(uint32_t opcode, uint32_t address, arm_instruction_t *instruct
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/* Coprocessor load/store and double register transfers */
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/* both normal and extended instruction space (condition field b1111) */
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int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t cp_num = (opcode & 0xf00) >> 8;
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@ -222,9 +292,10 @@ int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, uint32_t address, arm_instructio
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/* Coprocessor data processing instructions */
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/* Coprocessor register transfer instructions */
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/* both normal and extended instruction space (condition field b1111) */
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int evaluate_cdp_mcr_mrc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_cdp_mcr_mrc(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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char* cond;
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const char *cond;
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char* mnemonic;
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uint8_t cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2;
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@ -271,7 +342,8 @@ int evaluate_cdp_mcr_mrc(uint32_t opcode, uint32_t address, arm_instruction_t *i
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}
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/* Load/store instructions */
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int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_load_store(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t I, P, U, B, W, L;
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uint8_t Rn, Rd;
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@ -445,9 +517,6 @@ static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp)
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unsigned rn = (opcode >> 16) & 0xf;
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char *type, *rot;
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/* GCC 'uninitialized warning removal' */
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type = rot = NULL;
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switch ((opcode >> 24) & 0x3) {
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case 0:
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type = "B16";
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@ -458,7 +527,7 @@ static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp)
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case 2:
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type = "B";
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break;
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case 3:
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default:
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type = "H";
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break;
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}
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@ -473,7 +542,7 @@ static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp)
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case 2:
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rot = ", ROR #16";
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break;
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case 3:
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default:
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rot = ", ROR #24";
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break;
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}
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@ -759,7 +828,8 @@ undef:
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}
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/* Miscellaneous load/store instructions */
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int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_misc_load_store(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t P, U, I, W, L, S, H;
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uint8_t Rn, Rd;
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@ -886,7 +956,8 @@ int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_
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}
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/* Load/store multiples instructions */
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int evaluate_ldm_stm(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_ldm_stm(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t P, U, S, W, L, Rn;
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uint32_t register_list;
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@ -974,7 +1045,8 @@ int evaluate_ldm_stm(uint32_t opcode, uint32_t address, arm_instruction_t *instr
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}
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/* Multiplies, extra load/stores */
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int evaluate_mul_and_extra_ld_st(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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/* Multiply (accumulate) (long) and Swap/swap byte */
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if ((opcode & 0x000000f0) == 0x00000090)
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@ -1065,7 +1137,8 @@ int evaluate_mul_and_extra_ld_st(uint32_t opcode, uint32_t address, arm_instruct
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return evaluate_misc_load_store(opcode, address, instruction);
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}
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int evaluate_mrs_msr(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_mrs_msr(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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int R = (opcode & 0x00400000) >> 22;
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char *PSR = (R) ? "SPSR" : "CPSR";
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@ -1119,7 +1192,8 @@ int evaluate_mrs_msr(uint32_t opcode, uint32_t address, arm_instruction_t *instr
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}
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/* Miscellaneous instructions */
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int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_misc_instr(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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/* MRS/MSR */
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if ((opcode & 0x000000f0) == 0x00000000)
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@ -1309,7 +1383,8 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
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return ERROR_OK;
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}
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int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_data_proc(uint32_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t I, op, S, Rn, Rd;
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char *mnemonic = NULL;
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@ -1668,7 +1743,8 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *in
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return -1;
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}
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int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_b_bl_blx_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint32_t offset = opcode & 0x7ff;
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uint32_t opc = (opcode >> 11) & 0x3;
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@ -1721,7 +1797,8 @@ int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
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return ERROR_OK;
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}
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int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_add_sub_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t Rd = (opcode >> 0) & 0x7;
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uint8_t Rn = (opcode >> 3) & 0x7;
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@ -1766,7 +1843,8 @@ int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
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return ERROR_OK;
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}
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int evaluate_shift_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_shift_imm_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t Rd = (opcode >> 0) & 0x7;
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uint8_t Rm = (opcode >> 3) & 0x7;
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@ -1811,7 +1889,8 @@ int evaluate_shift_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_
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return ERROR_OK;
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}
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int evaluate_data_proc_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_data_proc_imm_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t imm = opcode & 0xff;
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uint8_t Rd = (opcode >> 8) & 0x7;
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@ -1853,7 +1932,8 @@ int evaluate_data_proc_imm_thumb(uint16_t opcode, uint32_t address, arm_instruct
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return ERROR_OK;
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}
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int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_data_proc_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t high_reg, op, Rm, Rd,H1,H2;
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char *mnemonic = NULL;
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@ -2038,7 +2118,8 @@ static inline uint32_t thumb_alignpc4(uint32_t addr)
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return (addr + 4) & ~3;
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}
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int evaluate_load_literal_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_load_literal_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint32_t immediate;
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uint8_t Rd = (opcode >> 8) & 0x7;
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@ -2062,7 +2143,8 @@ int evaluate_load_literal_thumb(uint16_t opcode, uint32_t address, arm_instructi
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return ERROR_OK;
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}
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int evaluate_load_store_reg_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_load_store_reg_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint8_t Rd = (opcode >> 0) & 0x7;
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uint8_t Rn = (opcode >> 3) & 0x7;
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@ -2119,7 +2201,8 @@ int evaluate_load_store_reg_thumb(uint16_t opcode, uint32_t address, arm_instruc
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return ERROR_OK;
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}
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int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_load_store_imm_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint32_t offset = (opcode >> 6) & 0x1f;
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uint8_t Rd = (opcode >> 0) & 0x7;
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@ -2165,7 +2248,8 @@ int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruc
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return ERROR_OK;
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}
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int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_load_store_stack_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint32_t offset = opcode & 0xff;
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uint8_t Rd = (opcode >> 8) & 0x7;
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@ -2196,7 +2280,8 @@ int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instr
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return ERROR_OK;
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}
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int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_add_sp_pc_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint32_t imm = opcode & 0xff;
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uint8_t Rd = (opcode >> 8) & 0x7;
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@ -2229,7 +2314,8 @@ int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
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return ERROR_OK;
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}
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int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_adjust_stack_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint32_t imm = opcode & 0x7f;
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uint8_t opc = opcode & (1 << 7);
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@ -2259,7 +2345,8 @@ int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instructi
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return ERROR_OK;
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}
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int evaluate_breakpoint_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
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static int evaluate_breakpoint_thumb(uint16_t opcode,
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uint32_t address, arm_instruction_t *instruction)
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{
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uint32_t imm = opcode & 0xff;
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@ -2272,7 +2359,8 @@ int evaluate_breakpoint_thumb(uint16_t opcode, uint32_t address, arm_instruction
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return ERROR_OK;
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}
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int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
|
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static int evaluate_load_store_multiple_thumb(uint16_t opcode,
|
||||
uint32_t address, arm_instruction_t *instruction)
|
||||
{
|
||||
uint32_t reg_list = opcode & 0xff;
|
||||
uint32_t L = opcode & (1 << 11);
|
||||
|
|
@ -2285,6 +2373,10 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
|
|||
char ptr_name[7] = "";
|
||||
int i;
|
||||
|
||||
/* REVISIT: in ThumbEE mode, there are no LDM or STM instructions.
|
||||
* The STMIA and LDMIA opcodes are used for other instructions.
|
||||
*/
|
||||
|
||||
if ((opcode & 0xf000) == 0xc000)
|
||||
{ /* generic load/store multiple */
|
||||
char *wback = "!";
|
||||
|
|
@ -2345,7 +2437,8 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int evaluate_cond_branch_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
|
||||
static int evaluate_cond_branch_thumb(uint16_t opcode,
|
||||
uint32_t address, arm_instruction_t *instruction)
|
||||
{
|
||||
uint32_t offset = opcode & 0xff;
|
||||
uint8_t cond = (opcode >> 8) & 0xf;
|
||||
|
|
@ -2835,6 +2928,12 @@ static int t2ev_misc(uint32_t opcode, uint32_t address,
|
|||
const char *mnemonic;
|
||||
|
||||
switch ((opcode >> 4) & 0x0f) {
|
||||
case 0:
|
||||
mnemonic = "LEAVEX";
|
||||
break;
|
||||
case 1:
|
||||
mnemonic = "ENTERX";
|
||||
break;
|
||||
case 2:
|
||||
mnemonic = "CLREX";
|
||||
break;
|
||||
|
|
@ -2888,6 +2987,9 @@ static int t2ev_b_misc(uint32_t opcode, uint32_t address,
|
|||
return t2ev_hint(opcode, address, instruction, cp);
|
||||
case 0x3b:
|
||||
return t2ev_misc(opcode, address, instruction, cp);
|
||||
case 0x3c:
|
||||
sprintf(cp, "BXJ\tr%d", (int) (opcode >> 16) & 0x0f);
|
||||
return ERROR_OK;
|
||||
case 0x3e:
|
||||
case 0x3f:
|
||||
sprintf(cp, "MRS\tr%d, %s", (int) (opcode >> 8) & 0x0f,
|
||||
|
|
|
|||
Loading…
Reference in New Issue