- add support for hardware breakpoints to mips32 target

git-svn-id: svn://svn.berlios.de/openocd/trunk@1173 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/mips32.c

@@ -325,6 +325,10 @@ int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_p
 	target->arch_info = mips32;
 	mips32->common_magic = MIPS32_COMMON_MAGIC;
 	
+	/* has breakpoint/watchpint unit been scanned */
+	mips32->bp_scanned = 0;
+	mips32->data_break_list = NULL;
+	
 	mips32->ejtag_info.chain_pos = chain_pos;
 	mips32->read_core_reg = mips32_read_core_reg;
 	mips32->write_core_reg = mips32_write_core_reg;
@@ -342,3 +346,82 @@ int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
 	/*TODO*/
 	return ERROR_OK;
 }
+
+int mips32_examine(struct target_s *target)
+{
+	mips32_common_t *mips32 = target->arch_info;
+	
+	if (!target->type->examined)
+	{
+		target->type->examined = 1;
+	
+		/* we will configure later */
+		mips32->bp_scanned = 0;
+		mips32->num_inst_bpoints = 0;
+		mips32->num_data_bpoints = 0;
+		mips32->num_inst_bpoints_avail = 0;
+		mips32->num_data_bpoints_avail = 0;
+	}
+		
+	return ERROR_OK;
+}
+
+int mips32_configure_break_unit(struct target_s *target)
+{
+	/* get pointers to arch-specific information */
+	mips32_common_t *mips32 = target->arch_info;
+	int retval;
+	u32 dcr, bpinfo;
+	int i;
+	
+	if (mips32->bp_scanned)
+		return ERROR_OK;
+	
+	/* get info about breakpoint support */
+	if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
+		return retval;
+	
+	if (dcr & (1 << 16))
+	{
+		/* get number of inst breakpoints */
+		if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
+			return retval;
+		
+		mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
+		mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
+		mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(mips32_comparator_t));
+		for (i = 0; i < mips32->num_inst_bpoints; i++)
+		{
+			mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
+		}
+		
+		/* clear IBIS reg */
+		if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
+			return retval;
+	}
+	
+	if (dcr & (1 << 17))
+	{
+		/* get number of data breakpoints */
+		if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
+			return retval;
+		
+		mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
+		mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
+		mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(mips32_comparator_t));
+		for (i = 0; i < mips32->num_data_bpoints; i++)
+		{
+			mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
+		}
+		
+		/* clear DBIS reg */
+		if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
+			return retval;
+	}
+	
+	LOG_DEBUG("DCR 0x%x numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
+	
+	mips32->bp_scanned = 1;
+	
+	return ERROR_OK;
+}

src/target/mips32.h

@@ -37,6 +37,14 @@ enum
 	MIPS32NUMCOREREGS
 };
 
+typedef struct mips32_comparator_s
+{
+	int used;
+	//int type;
+	u32 bp_value;
+	u32 reg_address;
+} mips32_comparator_t;
+
 typedef struct mips32_common_s
 {
 	int common_magic;
@@ -45,6 +53,14 @@ typedef struct mips32_common_s
 	mips_ejtag_t ejtag_info;
 	u32 core_regs[MIPS32NUMCOREREGS];
 	
+	int bp_scanned;
+	int num_inst_bpoints;
+	int num_data_bpoints;
+	int num_inst_bpoints_avail;
+	int num_data_bpoints_avail;
+	mips32_comparator_t *inst_break_list;
+	mips32_comparator_t *data_break_list;
+	
 	/* register cache to processor synchronization */
 	int (*read_core_reg)(struct target_s *target, int num);
 	int (*write_core_reg)(struct target_s *target, int num);
@@ -108,6 +124,8 @@ extern int mips32_restore_context(target_t *target);
 extern int mips32_save_context(target_t *target);
 extern reg_cache_t *mips32_build_reg_cache(target_t *target);
 extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+extern int mips32_configure_break_unit(struct target_s *target);
+extern int mips32_examine(struct target_s *target);
 
 extern int mips32_register_commands(struct command_context_s *cmd_ctx);
 extern int mips32_invalidate_core_regs(target_t *target);

src/target/mips_ejtag.c

@@ -227,6 +227,7 @@ int mips_ejtag_exit_debug(mips_ejtag_t *ejtag_info, int enable_interrupts)
 
 int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg)
 {
+	/* read ejtag ECR */
 	u32 code[] = {
 			MIPS32_MTC0(15,31,0),							/* move $15 to COP0 DeSave */
 			MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), 	/* $15 = MIPS32_PRACC_STACK */
@@ -288,6 +289,7 @@ int mips_ejtag_init(mips_ejtag_t *ejtag_info)
 		ejtag_info->impcode & (1<<14) ? " noDMA":  " DMA",
 		ejtag_info->impcode & (1<<0)  ? " MIPS64": " MIPS32"
 	);
+	
 	if((ejtag_info->impcode & (1<<14)) == 0)
 		LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
 	

src/target/mips_ejtag.h

@@ -41,7 +41,7 @@
 #define EJTAG_INST_TCBDATA		0x12
 #define EJTAG_INST_BYPASS		0xFF
 
-/* debug control register bits */
+/* debug control register bits ECR */
 #define EJTAG_CTRL_TOF			(1 << 1)
 #define EJTAG_CTRL_TIF			(1 << 2)
 #define EJTAG_CTRL_BRKST		(1 << 3)
@@ -91,6 +91,13 @@
 #define EJTAG_IMP_NODMA			(1 << 14)
 #define EJTAG_IMP_MIPS16		(1 << 16)
 
+/* breakpoint support */
+#define EJTAG_DCR				0xFF300000
+#define EJTAG_IBS				0xFF301000
+#define EJTAG_IBA1				0xFF301100
+#define EJTAG_DBS				0xFF302000
+#define EJTAG_DBA1				0xFF302100
+
 typedef struct mips_ejtag_s
 {
 	int chain_pos;

src/target/mips_m4k.c

@@ -90,28 +90,56 @@ target_type_t mips_m4k_target =
 	.quit = mips_m4k_quit
 };
 
-int mips_m4k_debug_entry(target_t *target)
+int mips_m4k_examine_debug_reason(target_t *target)
 {	
-	u32 debug_reg;
+	int break_status;
-	mips32_common_t *mips32 = target->arch_info;
+	int retval;
-	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-	
-	/* read debug register */
-	mips_ejtag_read_debug(ejtag_info, &debug_reg);
 	
 	if ((target->debug_reason != DBG_REASON_DBGRQ)
 		&& (target->debug_reason != DBG_REASON_SINGLESTEP))
 	{
-//		if (cortex_m3->nvic_dfsr & DFSR_BKPT)
+		/* get info about inst breakpoint support */
-//		{
+		if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
-//			target->debug_reason = DBG_REASON_BREAKPOINT;
+			return retval;
-//			if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
+		if (break_status & 0x1f)
-//				target->debug_reason = DBG_REASON_WPTANDBKPT;
+		{
-//		}
+			/* we have halted on a  breakpoint */
-//		else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
+			if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
-//			target->debug_reason = DBG_REASON_WATCHPOINT;
+				return retval;
+			target->debug_reason = DBG_REASON_BREAKPOINT;
 		}
 		
+		/* get info about data breakpoint support */
+		if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
+			return retval;
+		if (break_status & 0x1f)
+		{
+			/* we have halted on a  breakpoint */
+			if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
+				return retval;
+			target->debug_reason = DBG_REASON_WATCHPOINT;
+		}
+	}
+	
+	return ERROR_OK;
+}
+
+int mips_m4k_debug_entry(target_t *target)
+{
+	mips32_common_t *mips32 = target->arch_info;
+	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+	u32 debug_reg;
+	
+	/* read debug register */
+	mips_ejtag_read_debug(ejtag_info, &debug_reg);
+	
+	/* make sure break uit configured */
+	mips32_configure_break_unit(target);
+	
+	/* attempt to find halt reason */
+	mips_m4k_examine_debug_reason(target);
+	
+	/* clear single step if active */
 	if (debug_reg & EJTAG_DEBUG_DSS)
 	{
 		/* stopped due to single step - clear step bit */
@@ -312,6 +340,22 @@ int mips_m4k_soft_reset_halt(struct target_s *target)
 	return ERROR_OK;
 }
 
+int mips_m4k_single_step_core(target_t *target)
+{
+	mips32_common_t *mips32 = target->arch_info;
+	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+	
+	/* configure single step mode */
+	mips_ejtag_config_step(ejtag_info, 1);
+	
+	/* exit debug mode */
+	mips_ejtag_exit_debug(ejtag_info, 1);
+	
+	mips_m4k_debug_entry(target);
+	
+	return ERROR_OK;
+}
+
 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
 {
 	mips32_common_t *mips32 = target->arch_info;
@@ -352,13 +396,14 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl
 		{
 			LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
 			mips_m4k_unset_breakpoint(target, breakpoint);
-			//mips_m4k_single_step_core(target);
+			mips_m4k_single_step_core(target);
 			mips_m4k_set_breakpoint(target, breakpoint);
 		}
 	}
 	
 	/* exit debug mode - enable interrupts if required */
 	mips_ejtag_exit_debug(ejtag_info, !debug_execution);
+	target->debug_reason = DBG_REASON_NOTHALTED;
 	
 	/* registers are now invalid */
 	mips32_invalidate_core_regs(target);
@@ -443,25 +488,114 @@ void mips_m4k_enable_breakpoints(struct target_s *target)
 
 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
-	/* TODO */
+	mips32_common_t *mips32 = target->arch_info;
+	mips32_comparator_t * comparator_list = mips32->inst_break_list;
+	
+	if (breakpoint->set)
+	{
+		LOG_WARNING("breakpoint already set");
+		return ERROR_OK;
+	}
+	
+	if (breakpoint->type == BKPT_HARD)
+	{
+		int bp_num = 0;
+		
+		while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
+			bp_num++;
+		if (bp_num >= mips32->num_inst_bpoints)
+		{
+			LOG_DEBUG("ERROR Can not find free FP Comparator");
+			LOG_WARNING("ERROR Can not find free FP Comparator");
+			exit(-1);
+		}
+		breakpoint->set = bp_num + 1;
+		comparator_list[bp_num].used = 1;
+		comparator_list[bp_num].bp_value = breakpoint->address;
+		target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
+		target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
+		target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
+		LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
+	}
+	else if (breakpoint->type == BKPT_SOFT)
+	{
+
+	}
+	
 	return ERROR_OK;
 }
 
 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
-	/* TODO */
+	/* get pointers to arch-specific information */
+	mips32_common_t *mips32 = target->arch_info;
+	mips32_comparator_t * comparator_list = mips32->inst_break_list;
+
+	if (!breakpoint->set)
+	{
+		LOG_WARNING("breakpoint not set");
+		return ERROR_OK;
+	}
+	
+	if (breakpoint->type == BKPT_HARD)
+	{
+		int bp_num = breakpoint->set - 1;
+		if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
+		{
+			LOG_DEBUG("Invalid FP Comparator number in breakpoint");
+			return ERROR_OK;
+		}
+		comparator_list[bp_num].used = 0;
+		comparator_list[bp_num].bp_value = 0;
+		target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
+	}
+	else
+	{
+
+	}
+	breakpoint->set = 0;
+	
 	return ERROR_OK;
 }
 
 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
-	/* TODO */
+	mips32_common_t *mips32 = target->arch_info;
+	
+	if (mips32->num_inst_bpoints_avail < 1)
+	{
+		LOG_INFO("no hardware breakpoint available");
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+	
+	/* default to hardware for now */
+	breakpoint->type = BKPT_HARD;
+	
+	mips32->num_inst_bpoints_avail--;
+	mips_m4k_set_breakpoint(target, breakpoint);
+	
 	return ERROR_OK;
 }
 
 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
-	/* TODO */
+	/* get pointers to arch-specific information */
+	mips32_common_t *mips32 = target->arch_info;
+	
+	if (target->state != TARGET_HALTED)
+	{
+		LOG_WARNING("target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+	
+	if (breakpoint->set)
+	{
+		mips_m4k_unset_breakpoint(target, breakpoint);
+	}
+	
+	if (breakpoint->type == BKPT_HARD)
+		mips32->num_inst_bpoints_avail++;
+	
 	return ERROR_OK;
 }
 
@@ -639,8 +773,8 @@ int mips_m4k_examine(struct target_s *target)
 	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 	u32 idcode = 0;
 	
-	target->type->examined = 1;
+	if (!target->type->examined)
-	
+	{
 		mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
 		
 		if (((idcode >> 1) & 0x7FF) == 0x29)
@@ -650,11 +784,15 @@ int mips_m4k_examine(struct target_s *target)
 			mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
 			LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
 		}
+	}
 	
 	/* init rest of ejtag interface */
 	if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
 		return retval;
 	
+	if ((retval = mips32_examine(target)) != ERROR_OK)
+		return retval;
+	
 	return ERROR_OK;
 }