zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: simplify CPSR handling 

Stash a pointer to the CPSR in the "struct arm", to help get rid
of the (common) references to its index in the register cache.

This removes almost all references to CPSR offsets outside of the
toplevel ARM code ... except a pair related to the current ARM11
"simulator" logic (which should be removable soonish).

This is a net minor code shrink of a few hundred bytes of object
code, and also makes the code more readable.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
__archive__
David Brownell 2009-11-22 03:37:21 -08:00
parent 60a2d85af1
commit 5706fd7860
11 changed files with 103 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/target/arm720t.c
View File

@ -240,7 +240,7 @@ static int arm720t_arch_state(struct target *target)
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm720t->armv4_5_mmu.mmu_enabled],
state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
@ -347,9 +347,9 @@ static int arm720t_soft_reset_halt(struct target *target)
target->state = TARGET_HALTED;
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
armv4_5->cpsr->dirty = 1;
armv4_5->cpsr->valid = 1;
/* start fetching from 0x0 */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);

59
src/target/arm7_9_common.c
View File

@ -1227,9 +1227,9 @@ int arm7_9_soft_reset_halt(struct target *target)
register_cache_invalidate(armv4_5->core_cache);
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
armv4_5->cpsr->dirty = 1;
armv4_5->cpsr->valid = 1;
/* start fetching from 0x0 */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
@ -1401,9 +1401,9 @@ static int arm7_9_debug_entry(struct target *target)
if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
cpsr |= 0x20;
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
buf_set_u32(armv4_5->cpsr->value, 0, 32, cpsr);
armv4_5->cpsr->dirty = 0;
armv4_5->cpsr->valid = 1;
armv4_5->core_mode = cpsr & 0x1f;
@ -1520,7 +1520,8 @@ int arm7_9_full_context(struct target *target)
uint32_t tmp_cpsr;
/* change processor mode (and mask T bit) */
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
& 0xe0;
tmp_cpsr |= armv4_5_number_to_mode(i);
tmp_cpsr &= ~0x20;
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@ -1551,7 +1552,9 @@ int arm7_9_full_context(struct target *target)
}
/* restore processor mode (mask T bit) */
arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
0, 0);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -1645,7 +1648,8 @@ int arm7_9_restore_context(struct target *target)
uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
0, 8) & 0xe0;
tmp_cpsr |= armv4_5_number_to_mode(i);
tmp_cpsr &= ~0x20;
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@ -1687,24 +1691,27 @@ int arm7_9_restore_context(struct target *target)
}
}
if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
{
/* restore processor mode (mask T bit) */
uint32_t tmp_cpsr;
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
tmp_cpsr |= armv4_5_number_to_mode(i);
tmp_cpsr &= ~0x20;
LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
}
else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
else if (armv4_5->cpsr->dirty)
{
/* CPSR has been changed, full restore necessary (mask T bit) */
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
buf_get_u32(armv4_5->cpsr->value, 0, 32));
arm7_9->write_xpsr(target,
buf_get_u32(armv4_5->cpsr->value, 0, 32)
& ~0x20, 0);
armv4_5->cpsr->dirty = 0;
armv4_5->cpsr->valid = 1;
}
/* restore PC */
@ -2106,7 +2113,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
tmp_cpsr |= mode;
tmp_cpsr &= ~0x20;
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@ -2140,7 +2147,9 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
&& (mode != armv4_5->core_mode)
&& (areg->mode != ARMV4_5_MODE_ANY)) {
/* restore processor mode (mask T bit) */
arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
& ~0x20, 0, 0);
}
return ERROR_OK;
@ -2165,7 +2174,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
tmp_cpsr |= mode;
tmp_cpsr &= ~0x20;
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@ -2199,7 +2208,9 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
&& (mode != armv4_5->core_mode)
&& (areg->mode != ARMV4_5_MODE_ANY)) {
/* restore processor mode (mask T bit) */
arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
& ~0x20, 0, 0);
}
return jtag_execute_queue();
@ -2372,7 +2383,9 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
{
LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
& ~0x20, 0, 0);
return ERROR_TARGET_DATA_ABORT;
}
@ -2555,7 +2568,9 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
{
LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
& ~0x20, 0, 0);
return ERROR_TARGET_DATA_ABORT;
}

8
src/target/arm920t.c
View File

@ -452,7 +452,7 @@ int arm920t_arch_state(struct target *target)
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm920t->armv4_5_mmu.mmu_enabled],
state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
@ -596,9 +596,9 @@ int arm920t_soft_reset_halt(struct target *target)
target->state = TARGET_HALTED;
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
armv4_5->cpsr->dirty = 1;
armv4_5->cpsr->valid = 1;
/* start fetching from 0x0 */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);

8
src/target/arm926ejs.c
View File

@ -510,7 +510,7 @@ int arm926ejs_arch_state(struct target *target)
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm926ejs->armv4_5_mmu.mmu_enabled],
state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
@ -565,9 +565,9 @@ int arm926ejs_soft_reset_halt(struct target *target)
target->state = TARGET_HALTED;
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
armv4_5->cpsr->dirty = 1;
armv4_5->cpsr->valid = 1;
/* start fetching from 0x0 */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);

2
src/target/arm_simulator.c
View File

@ -821,7 +821,7 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
return buf_get_u32(armv4_5->cpsr->value, pos, bits);
}
static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)

38
src/target/armv4_5.c
View File

@ -36,6 +36,17 @@
#include "register.h"
/* offsets into armv4_5 core register cache */
enum {
// ARMV4_5_CPSR = 31,
ARMV4_5_SPSR_FIQ = 32,
ARMV4_5_SPSR_IRQ = 33,
ARMV4_5_SPSR_SVC = 34,
ARMV4_5_SPSR_ABT = 35,
ARMV4_5_SPSR_UND = 36,
ARM_SPSR_MON = 39,
};
static const uint8_t arm_usr_indices[17] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
};
@ -214,7 +225,7 @@ char* armv4_5_state_strings[] =
*
* NOTE: offsets in this table are coupled to the arm_mode_data
* table above, the armv4_5_core_reg_map array below, and also to
* the ARMV4_5_*PSR* symols.
* the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
*/
static const struct {
/* The name is used for e.g. the "regs" command. */
@ -401,7 +412,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
reg->dirty = 1;
reg->valid = 1;
if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
if (reg == armv4_5_target->cpsr)
{
/* FIXME handle J bit too; mostly for ThumbEE, also Jazelle */
if (value & 0x20)
@ -493,6 +504,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
cache->num_regs++;
}
armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
armv4_5_common->core_cache = cache;
return cache;
}
@ -511,7 +523,7 @@ int armv4_5_arch_state(struct target *target)
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
return ERROR_OK;
@ -750,7 +762,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
}
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
(*reg_list)[25] = armv4_5->cpsr;
return ERROR_OK;
}
@ -834,7 +846,7 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
armv4_5_algorithm_info->core_mode);
context[i] = buf_get_u32(r->value, 0, 32);
}
cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
for (i = 0; i < num_mem_params; i++)
{
@ -878,10 +890,12 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
{
LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
LOG_DEBUG("setting core_mode: 0x%2.2x",
armv4_5_algorithm_info->core_mode);
buf_set_u32(armv4_5->cpsr->value, 0, 5,
armv4_5_algorithm_info->core_mode);
armv4_5->cpsr->dirty = 1;
armv4_5->cpsr->valid = 1;
}
/* terminate using a hardware or (ARMv5+) software breakpoint */
@ -950,9 +964,9 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
}
}
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
buf_set_u32(armv4_5->cpsr->value, 0, 32, cpsr);
armv4_5->cpsr->valid = 1;
armv4_5->cpsr->dirty = 1;
armv4_5->core_state = core_state;
armv4_5->core_mode = core_mode;

16
src/target/armv4_5.h
View File

@ -62,17 +62,8 @@ extern const int armv4_5_core_reg_map[8][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
/* offsets into armv4_5 core register cache */
enum
{
ARMV4_5_CPSR = 31,
ARMV4_5_SPSR_FIQ = 32,
ARMV4_5_SPSR_IRQ = 33,
ARMV4_5_SPSR_SVC = 34,
ARMV4_5_SPSR_ABT = 35,
ARMV4_5_SPSR_UND = 36,
ARM_SPSR_MON = 39,
};
/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
enum { ARMV4_5_CPSR = 31, };
#define ARMV4_5_COMMON_MAGIC 0x0A450A45
@ -91,6 +82,9 @@ struct arm
int common_magic;
struct reg_cache *core_cache;
/** Handle to the CPSR; valid in all core modes. */
struct reg *cpsr;
/**
* Indicates what registers are in the ARM state core register set.
* ARMV4_5_MODE_ANY indicates the standard set of 37 registers,

3
src/target/armv7a.c
View File

@ -74,8 +74,7 @@ int armv7a_arch_state(struct target *target)
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache
->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[armv7a->armv4_5_mmu.mmu_enabled],
state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],

10
src/target/armv7a.h
View File

@ -30,16 +30,6 @@ enum
ARM_CPSR = 16
}
;
/* offsets into armv4_5 core register cache */
enum
{
ARMV7A_CPSR = 31,
ARMV7A_SPSR_FIQ = 32,
ARMV7A_SPSR_IRQ = 33,
ARMV7A_SPSR_SVC = 34,
ARMV7A_SPSR_ABT = 35,
ARMV7A_SPSR_UND = 36
};
#define ARMV7_COMMON_MAGIC 0x0A450999

12
src/target/cortex_a8.c
View File

@ -674,7 +674,7 @@ static int cortex_a8_debug_entry(struct target *target)
}
/* update cache */
reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
reg = armv4_5->cpsr;
buf_set_u32(reg->value, 0, 32, cpsr);
reg->valid = 1;
reg->dirty = 0;
@ -879,7 +879,7 @@ static int cortex_a8_restore_context(struct target *target)
for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
struct arm_reg *reg;
if (!r->dirty || i == ARMV4_5_CPSR)
if (!r->dirty || r == armv7a->armv4_5_common.cpsr)
continue;
reg = r->arch_info;
@ -915,7 +915,7 @@ static int cortex_a8_restore_context(struct target *target)
} while (flushed);
/* now flush CPSR if needed ... */
r = cache->reg_list + ARMV4_5_CPSR;
r = armv7a->armv4_5_common.cpsr;
if (flush_cpsr || r->dirty) {
value = buf_get_u32(r->value, 0, 32);
cortex_a8_dap_write_coreregister_u32(target, value, 16);
@ -1027,7 +1027,6 @@ static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
uint32_t value;
int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
struct reg_cache *cache = armv4_5->core_cache;
struct reg *cpsr_r = NULL;
uint32_t cpsr = 0;
unsigned cookie = num;
@ -1043,7 +1042,7 @@ static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
mode = ARMV4_5_MODE_ANY;
if (mode != ARMV4_5_MODE_ANY) {
cpsr_r = cache->reg_list + ARMV4_5_CPSR;
cpsr_r = armv4_5->cpsr;
cpsr = buf_get_u32(cpsr_r->value, 0, 32);
cortex_a8_write_core_reg(target, cpsr_r,
16, ARMV4_5_MODE_ANY, mode);
@ -1083,7 +1082,6 @@ static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
{
int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
struct reg_cache *cache = armv4_5->core_cache;
struct reg *cpsr_r = NULL;
uint32_t cpsr = 0;
unsigned cookie = num;
@ -1099,7 +1097,7 @@ static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
mode = ARMV4_5_MODE_ANY;
if (mode != ARMV4_5_MODE_ANY) {
cpsr_r = cache->reg_list + ARMV4_5_CPSR;
cpsr_r = armv4_5->cpsr;
cpsr = buf_get_u32(cpsr_r->value, 0, 32);
cortex_a8_write_core_reg(target, cpsr_r,
16, ARMV4_5_MODE_ANY, mode);

26
src/target/xscale.c
View File

@ -858,7 +858,7 @@ static int xscale_arch_state(struct target *target)
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[xscale->armv4_5_mmu.mmu_enabled],
state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
@ -948,9 +948,9 @@ static int xscale_debug_entry(struct target *target)
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
}
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
buf_set_u32(armv4_5->cpsr->value, 0, 32, buffer[9]);
armv4_5->cpsr->dirty = 1;
armv4_5->cpsr->valid = 1;
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
armv4_5->core_mode = buffer[9] & 0x1f;
@ -1260,8 +1260,10 @@ static int xscale_resume(struct target *target, int current,
xscale_send_u32(target, 0x30);
/* send CPSR */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
xscale_send_u32(target,
buf_get_u32(armv4_5->cpsr->value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
buf_get_u32(armv4_5->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--)
{
@ -1303,8 +1305,9 @@ static int xscale_resume(struct target *target, int current,
xscale_send_u32(target, 0x30);
/* send CPSR */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
buf_get_u32(armv4_5->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--)
{
@ -1381,9 +1384,12 @@ static int xscale_step_inner(struct target *target, int current,
return retval;
/* send CPSR */
if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
retval = xscale_send_u32(target,
buf_get_u32(armv4_5->cpsr->value, 0, 32));
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
buf_get_u32(armv4_5->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--)
{