ARMv7A: use standard disassembler

We no longer need v7A-specific code for this.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
__archive__
David Brownell 2009-11-16 16:36:21 -08:00
parent d7d857a189
commit 56adbaffd0
2 changed files with 8 additions and 101 deletions

View File

@ -5535,10 +5535,17 @@ that is not currently supported in OpenOCD.)
Disassembles @var{count} instructions starting at @var{address}. Disassembles @var{count} instructions starting at @var{address}.
If @var{count} is not specified, a single instruction is disassembled. If @var{count} is not specified, a single instruction is disassembled.
If @option{thumb} is specified, or the low bit of the address is set, If @option{thumb} is specified, or the low bit of the address is set,
Thumb (16-bit) instructions are used; Thumb2 (mixed 16/32-bit) instructions are used;
else ARM (32-bit) instructions are used. else ARM (32-bit) instructions are used.
(Processors may also support the Jazelle state, but (Processors may also support the Jazelle state, but
those instructions are not currently understood by OpenOCD.) those instructions are not currently understood by OpenOCD.)
Note that all Thumb instructions are Thumb2 instructions,
so older processors (without Thumb2 support) will still
see correct disassembly of Thumb code.
Also, ThumbEE opcodes are the same as Thumb2,
with a handful of exceptions.
ThumbEE disassembly currently has no explicit support.
@end deffn @end deffn
@deffn Command {arm reg} @deffn Command {arm reg}
@ -5941,23 +5948,6 @@ Displays the number of extra tck for mem-ap memory bus access [0-255].
If @var{value} is defined, first assigns that. If @var{value} is defined, first assigns that.
@end deffn @end deffn
@subsection ARMv7-A specific commands
@cindex ARMv7-A
@deffn Command {armv7a disassemble} address [count [@option{thumb}]]
@cindex disassemble
Disassembles @var{count} instructions starting at @var{address}.
If @var{count} is not specified, a single instruction is disassembled.
If @option{thumb} is specified, or the low bit of the address is set,
Thumb2 (mixed 16/32-bit) instructions are used;
else ARM (32-bit) instructions are used.
With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
ThumbEE disassembly currently has no explicit support.
(Processors may also support the Jazelle state, but
those instructions are not currently understood by OpenOCD.)
@end deffn
@subsection Cortex-M3 specific commands @subsection Cortex-M3 specific commands
@cindex Cortex-M3 @cindex Cortex-M3

View File

@ -274,84 +274,9 @@ COMMAND_HANDLER(handle_dap_info_command)
return dap_info_command(cmd_ctx, swjdp, apsel); return dap_info_command(cmd_ctx, swjdp, apsel);
} }
COMMAND_HANDLER(handle_armv7a_disassemble_command)
{
struct target *target = get_current_target(cmd_ctx);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int thumb = 0;
int count = 1;
uint32_t address;
int i;
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) {
command_print(cmd_ctx, "current target isn't an ARM target");
return ERROR_OK;
}
/* REVISIT: eventually support ThumbEE disassembly too;
* some opcodes work differently.
*/
switch (argc) {
case 3:
if (strcmp(args[2], "thumb") != 0)
goto usage;
thumb = 1;
/* FALL THROUGH */
case 2:
COMMAND_PARSE_NUMBER(int, args[1], count);
/* FALL THROUGH */
case 1:
COMMAND_PARSE_NUMBER(u32, args[0], address);
if (address & 0x01) {
if (!thumb) {
command_print(cmd_ctx, "Disassemble as Thumb");
thumb = 1;
}
address &= ~1;
}
break;
default:
usage:
command_print(cmd_ctx,
"usage: armv7a disassemble <address> [<count> ['thumb']]");
return ERROR_OK;
}
for (i = 0; i < count; i++) {
struct arm_instruction cur_instruction;
int retval;
if (thumb) {
retval = thumb2_opcode(target, address, &cur_instruction);
if (retval != ERROR_OK)
return retval;
address += cur_instruction.instruction_size;
} else {
uint32_t opcode;
retval = target_read_u32(target, address, &opcode);
if (retval != ERROR_OK)
return retval;
retval = arm_evaluate_opcode(opcode, address,
&cur_instruction);
if (retval != ERROR_OK)
return retval;
address += 4;
}
command_print(cmd_ctx, "%s", cur_instruction.text);
}
return ERROR_OK;
}
int armv7a_register_commands(struct command_context *cmd_ctx) int armv7a_register_commands(struct command_context *cmd_ctx)
{ {
struct command *arm_adi_v5_dap_cmd; struct command *arm_adi_v5_dap_cmd;
struct command *armv7a_cmd;
arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
NULL, COMMAND_ANY, NULL, COMMAND_ANY,
@ -377,13 +302,5 @@ int armv7a_register_commands(struct command_context *cmd_ctx)
"set/get number of extra tck for mem-ap memory " "set/get number of extra tck for mem-ap memory "
"bus access [0-255]"); "bus access [0-255]");
armv7a_cmd = register_command(cmd_ctx, NULL, "armv7a",
NULL, COMMAND_ANY,
"ARMv7-A specific commands");
register_command(cmd_ctx, armv7a_cmd, "disassemble",
handle_armv7a_disassemble_command, COMMAND_EXEC,
"disassemble instructions <address> [<count> ['thumb']]");
return ERROR_OK; return ERROR_OK;
} }