target/imx7ulp: Initial support

Unlike imx7d/solo supported by imx7.cfg the M4 core is on a different AP
and is always running by default so no -defer-examine is required.

There is also only one Cortex-A7

Tested on imx7ulp-evk

Change-Id: Ifa923d1b9a372c788e6654bc2233fd4d9073a32d
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-on: http://openocd.zylin.com/5043
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
bscan_optimization
Leonard Crestez 2019-04-04 22:40:21 +03:00 committed by Matthias Welwarsky
parent ae4b2720a4
commit 537bbefcbd
1 changed files with 36 additions and 0 deletions

36
tcl/target/imx7ulp.cfg Normal file
View File

@ -0,0 +1,36 @@
#
# NXP i.MX7ULP: Cortex-A7 + Cortex-M4
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx7ulp
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
# TAPID is from FreeScale!
set _DAP_TAPID 0x188e101d
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# Cortex-A7
target create $_CHIPNAME.cpu_a7 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80030000
# Cortex-M4
# Boots by default so don't defer examination
target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap -ap-num 3
# AHB main soc bus
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
# Default is Cortex-A7
targets $_CHIPNAME.cpu_a7