aarch64: Implement MA mode for bulk memory reads and writes
- 64bit addresses are supported - Aarch32 state is supported Change-Id: I8c37fa166954d09195d08c6963b8017194e350f5 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>gitignore-build
Matthias Welwarsky
parent
db97bb4a9d
commit
53573f7860
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@ -26,7 +26,7 @@
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#include "register.h"
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#include "target_request.h"
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#include "target_type.h"
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#include "arm_opcodes.h"
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#include "armv8_opcodes.h"
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#include <helper/time_support.h>
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static int aarch64_poll(struct target *target);
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@ -43,7 +43,7 @@ static int aarch64_unset_breakpoint(struct target *target,
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static int aarch64_mmu(struct target *target, int *enabled);
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static int aarch64_virt2phys(struct target *target,
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target_addr_t virt, target_addr_t *phys);
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static int aarch64_read_apb_ab_memory(struct target *target,
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static int aarch64_read_apb_ap_memory(struct target *target,
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uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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static int aarch64_instr_write_data_r0(struct arm_dpm *dpm,
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uint32_t opcode, uint32_t data);
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@ -1673,7 +1673,7 @@ static int aarch64_deassert_reset(struct target *target)
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return ERROR_OK;
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}
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static int aarch64_write_apb_ab_memory(struct target *target,
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static int aarch64_write_apb_ap_memory(struct target *target,
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uint64_t address, uint32_t size,
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uint32_t count, const uint8_t *buffer)
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{
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@ -1688,7 +1688,6 @@ static int aarch64_write_apb_ab_memory(struct target *target,
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struct reg *reg;
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uint32_t dscr;
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uint8_t *tmp_buff = NULL;
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uint32_t i = 0;
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LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx64 " size %" PRIu32 " count%" PRIu32,
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address, size, count);
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@ -1711,15 +1710,13 @@ static int aarch64_write_apb_ab_memory(struct target *target,
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reg->dirty = true;
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/* clear any abort */
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retval = mem_ap_write_atomic_u32(armv8->debug_ap, armv8->debug_base + CPUDBG_DRCR, 1<<2);
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DRCR, DRCR_CSE);
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if (retval != ERROR_OK)
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return retval;
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/* This algorithm comes from either :
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* Cortex-A8 TRM Example 12-25
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* Cortex-R4 TRM Example 11-26
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* (slight differences)
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*/
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/* This algorithm comes from DDI0487A.g, chapter J9.1 */
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/* The algorithm only copies 32 bit words, so the buffer
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* should be expanded to include the words at either end.
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@ -1732,7 +1729,7 @@ static int aarch64_write_apb_ab_memory(struct target *target,
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/* First bytes not aligned - read the 32 bit word to avoid corrupting
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* the other bytes in the word.
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*/
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retval = aarch64_read_apb_ab_memory(target, (address & ~0x3), 4, 1, tmp_buff);
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retval = aarch64_read_apb_ap_memory(target, (address & ~0x3), 4, 1, tmp_buff);
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if (retval != ERROR_OK)
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goto error_free_buff_w;
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}
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@ -1743,7 +1740,7 @@ static int aarch64_write_apb_ab_memory(struct target *target,
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/* Read the last word to avoid corruption during 32 bit write */
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int mem_offset = (total_u32-1) * 4;
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retval = aarch64_read_apb_ab_memory(target, (address & ~0x3) + mem_offset, 4, 1, &tmp_buff[mem_offset]);
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retval = aarch64_read_apb_ap_memory(target, (address & ~0x3) + mem_offset, 4, 1, &tmp_buff[mem_offset]);
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if (retval != ERROR_OK)
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goto error_free_buff_w;
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}
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@ -1759,48 +1756,54 @@ static int aarch64_write_apb_ab_memory(struct target *target,
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if (retval != ERROR_OK)
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goto error_free_buff_w;
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/* Set DTR mode to Normal*/
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dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_NON_BLOCKING;
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/* Set Normal access mode */
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dscr = (dscr & ~DSCR_MA);
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, dscr);
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if (arm->core_state == ARM_STATE_AARCH64) {
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/* Write X0 with value 'address' using write procedure */
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/* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
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retval += aarch64_write_dcc_64(armv8, address & ~0x3ULL);
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/* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
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retval += aarch64_exec_opcode(target,
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ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
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} else {
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/* Write R0 with value 'address' using write procedure */
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/* Step 1.a+b - Write the address for read access into DBGDTRRX */
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retval += aarch64_write_dcc(armv8, address & ~0x3ULL);
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/* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
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retval += aarch64_exec_opcode(target,
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T32_FMTITR(ARMV4_5_MRC(14, 0, 0, 0, 5, 0)), &dscr);
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}
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/* Step 1.d - Change DCC to memory mode */
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dscr = dscr | DSCR_MA;
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retval += mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, dscr);
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if (retval != ERROR_OK)
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goto error_unset_dtr_w;
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/* Step 2.a - Do the write */
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retval = mem_ap_write_buf_noincr(armv8->debug_ap,
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tmp_buff, 4, total_u32, armv8->debug_base + CPUDBG_DTRRX);
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if (retval != ERROR_OK)
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goto error_unset_dtr_w;
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/* Step 3.a - Switch DTR mode back to Normal mode */
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dscr = (dscr & ~DSCR_MA);
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, dscr);
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if (retval != ERROR_OK)
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goto error_free_buff_w;
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if (size > 4) {
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LOG_WARNING("reading size >4 bytes not yet supported");
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goto error_unset_dtr_w;
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}
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retval = aarch64_instr_write_data_dcc_64(arm->dpm, 0xd5330401, address+4);
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if (retval != ERROR_OK)
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goto error_unset_dtr_w;
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dscr = DSCR_INSTR_COMP;
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while (i < count * size) {
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uint32_t val;
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memcpy(&val, &buffer[i], size);
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retval = aarch64_instr_write_data_dcc(arm->dpm, 0xd5330500, val);
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if (retval != ERROR_OK)
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goto error_unset_dtr_w;
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retval = aarch64_exec_opcode(target, 0xb81fc020, &dscr);
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if (retval != ERROR_OK)
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goto error_unset_dtr_w;
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retval = aarch64_exec_opcode(target, 0x91001021, &dscr);
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if (retval != ERROR_OK)
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goto error_unset_dtr_w;
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i += 4;
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}
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/* Check for sticky abort flags in the DSCR */
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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goto error_free_buff_w;
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if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
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if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
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/* Abort occurred - clear it and exit */
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LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
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mem_ap_write_atomic_u32(armv8->debug_ap,
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@ -1816,7 +1819,7 @@ error_unset_dtr_w:
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/* Unset DTR mode */
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mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, &dscr);
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dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_NON_BLOCKING;
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dscr = (dscr & ~DSCR_MA);
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mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, dscr);
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error_free_buff_w:
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@ -1825,19 +1828,23 @@ error_free_buff_w:
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return ERROR_FAIL;
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}
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static int aarch64_read_apb_ab_memory(struct target *target,
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static int aarch64_read_apb_ap_memory(struct target *target,
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target_addr_t address, uint32_t size,
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uint32_t count, uint8_t *buffer)
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{
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/* read memory through APB-AP */
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int retval = ERROR_COMMAND_SYNTAX_ERROR;
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm *arm = &armv8->arm;
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int total_bytes = count * size;
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int total_u32;
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int start_byte = address & 0x3;
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int end_byte = (address + total_bytes) & 0x3;
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struct reg *reg;
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uint32_t dscr, val;
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uint32_t dscr;
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uint8_t *tmp_buff = NULL;
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uint32_t i = 0;
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uint8_t *u8buf_ptr;
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uint32_t value;
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LOG_DEBUG("Reading APB-AP memory address 0x%" TARGET_PRIxADDR " size %" PRIu32 " count%" PRIu32,
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address, size, count);
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@ -1846,72 +1853,146 @@ static int aarch64_read_apb_ab_memory(struct target *target,
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return ERROR_TARGET_NOT_HALTED;
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}
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/* Mark register R0 as dirty, as it will be used
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total_u32 = DIV_ROUND_UP((address & 3) + total_bytes, 4);
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/* Mark register X0, X1 as dirty, as it will be used
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* for transferring the data.
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* It will be restored automatically when exiting
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* debug mode
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*/
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reg = armv8_reg_current(arm, 1);
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reg->dirty = true;
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reg = armv8_reg_current(arm, 0);
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reg->dirty = true;
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/* clear any abort */
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DRCR, 1<<2);
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armv8->debug_base + CPUDBG_DRCR, DRCR_CSE);
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if (retval != ERROR_OK)
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goto error_free_buff_r;
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/* Read DSCR */
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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goto error_unset_dtr_r;
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if (size > 4) {
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LOG_WARNING("reading size >4 bytes not yet supported");
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goto error_unset_dtr_r;
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/* This algorithm comes from DDI0487A.g, chapter J9.1 */
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/* Set Normal access mode */
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dscr = (dscr & ~DSCR_MA);
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retval += mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, dscr);
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if (arm->core_state == ARM_STATE_AARCH64) {
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/* Write X0 with value 'address' using write procedure */
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/* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
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retval += aarch64_write_dcc_64(armv8, address & ~0x3ULL);
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/* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
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retval += aarch64_exec_opcode(target, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
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/* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
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retval += aarch64_exec_opcode(target, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
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/* Step 1.e - Change DCC to memory mode */
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dscr = dscr | DSCR_MA;
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retval += mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, dscr);
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/* Step 1.f - read DBGDTRTX and discard the value */
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retval += mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DTRTX, &value);
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} else {
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/* Write R0 with value 'address' using write procedure */
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/* Step 1.a+b - Write the address for read access into DBGDTRRXint */
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retval += aarch64_write_dcc(armv8, address & ~0x3ULL);
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/* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
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retval += aarch64_exec_opcode(target,
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T32_FMTITR(ARMV4_5_MRC(14, 0, 0, 0, 5, 0)), &dscr);
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/* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
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retval += aarch64_exec_opcode(target,
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T32_FMTITR(ARMV4_5_MCR(14, 0, 0, 0, 5, 0)), &dscr);
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/* Step 1.e - Change DCC to memory mode */
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dscr = dscr | DSCR_MA;
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retval += mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, dscr);
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/* Step 1.f - read DBGDTRTX and discard the value */
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retval += mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DTRTX, &value);
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}
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while (i < count * size) {
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retval = aarch64_instr_write_data_dcc_64(arm->dpm, 0xd5330400, address+4);
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if (retval != ERROR_OK)
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goto error_unset_dtr_r;
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/* Optimize the read as much as we can, either way we read in a single pass */
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if ((start_byte) || (end_byte)) {
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/* The algorithm only copies 32 bit words, so the buffer
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* should be expanded to include the words at either end.
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* The first and last words will be read into a temp buffer
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* to avoid corruption
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*/
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tmp_buff = malloc(total_u32 * 4);
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if (!tmp_buff)
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goto error_unset_dtr_r;
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/* use the tmp buffer to read the entire data */
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u8buf_ptr = tmp_buff;
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} else
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/* address and read length are aligned so read directly into the passed buffer */
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u8buf_ptr = buffer;
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/* Read the data - Each read of the DTRTX register causes the instruction to be reissued
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* Abort flags are sticky, so can be read at end of transactions
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*
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* This data is read in aligned to 32 bit boundary.
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*/
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/* Step 2.a - Loop n-1 times, each read of DBGDTRTX reads the data from [X0] and
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* increments X0 by 4. */
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retval = mem_ap_read_buf_noincr(armv8->debug_ap, u8buf_ptr, 4, total_u32-1,
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armv8->debug_base + CPUDBG_DTRTX);
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if (retval != ERROR_OK)
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goto error_unset_dtr_r;
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/* Step 3.a - set DTR access mode back to Normal mode */
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dscr = (dscr & ~DSCR_MA);
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, dscr);
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if (retval != ERROR_OK)
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goto error_free_buff_r;
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/* Step 3.b - read DBGDTRTX for the final value */
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DTRTX, &value);
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memcpy(u8buf_ptr + (total_u32-1) * 4, &value, 4);
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/* Check for sticky abort flags in the DSCR */
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, &dscr);
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dscr = DSCR_INSTR_COMP;
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retval = aarch64_exec_opcode(target, 0xb85fc000, &dscr);
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if (retval != ERROR_OK)
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goto error_unset_dtr_r;
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, &dscr);
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retval = aarch64_instr_read_data_dcc(arm->dpm, 0xd5130400, &val);
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if (retval != ERROR_OK)
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goto error_unset_dtr_r;
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memcpy(&buffer[i], &val, size);
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i += 4;
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address += 4;
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}
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/* Clear any sticky error */
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goto error_free_buff_r;
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if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
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/* Abort occurred - clear it and exit */
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LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
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mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DRCR, 1<<2);
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armv8->debug_base + CPUDBG_DRCR, DRCR_CSE);
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goto error_free_buff_r;
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}
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/* check if we need to copy aligned data by applying any shift necessary */
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if (tmp_buff) {
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memcpy(buffer, tmp_buff + start_byte, total_bytes);
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free(tmp_buff);
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}
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/* Done */
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return ERROR_OK;
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error_unset_dtr_r:
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LOG_WARNING("DSCR = 0x%" PRIx32, dscr);
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/* Todo: Unset DTR mode */
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/* Unset DTR mode */
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mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, &dscr);
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dscr = (dscr & ~DSCR_MA);
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mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DSCR, dscr);
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error_free_buff_r:
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LOG_ERROR("error");
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free(tmp_buff);
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/* Clear any sticky error */
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mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUDBG_DRCR, 1<<2);
|
||||
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
|
|
@ -1937,7 +2018,7 @@ static int aarch64_read_phys_memory(struct target *target,
|
|||
retval = aarch64_mmu_modify(target, 0);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
retval = aarch64_read_apb_ab_memory(target, address, size, count, buffer);
|
||||
retval = aarch64_read_apb_ap_memory(target, address, size, count, buffer);
|
||||
}
|
||||
}
|
||||
return retval;
|
||||
|
|
@ -1988,7 +2069,7 @@ static int aarch64_read_memory(struct target *target, target_addr_t address,
|
|||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
retval = aarch64_read_apb_ab_memory(target, address, size,
|
||||
retval = aarch64_read_apb_ap_memory(target, address, size,
|
||||
count, buffer);
|
||||
}
|
||||
return retval;
|
||||
|
|
@ -2020,7 +2101,7 @@ static int aarch64_write_phys_memory(struct target *target,
|
|||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
return aarch64_write_apb_ab_memory(target, address, size, count, buffer);
|
||||
return aarch64_write_apb_ap_memory(target, address, size, count, buffer);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2128,7 +2209,7 @@ static int aarch64_write_memory(struct target *target, target_addr_t address,
|
|||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
retval = aarch64_write_apb_ab_memory(target, address, size, count, buffer);
|
||||
retval = aarch64_write_apb_ap_memory(target, address, size, count, buffer);
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue