parent
c68b13ed67
commit
526bbc5284
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@ -595,7 +595,9 @@ static int cache_check(struct target *target)
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return ERROR_OK;
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}
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/** Write cache to the target, and optionally run the program. */
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/** Write cache to the target, and optionally run the program.
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* Then read the value at address into the cache, assuming address < 128. */
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#define CACHE_NO_READ 128
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static int cache_write(struct target *target, unsigned int address, bool run)
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{
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LOG_DEBUG("enter");
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@ -633,17 +635,19 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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}
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}
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// Throw away the results of the first read, since it'll contain the result
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// of the read that happened just before debugint was set.
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add_dbus_scan(target, &field[scan], out + 8*scan, NULL, DBUS_OP_READ,
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address, DMCONTROL_HALTNOT);
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scan++;
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if (run || address < CACHE_NO_READ) {
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// Throw away the results of the first read, since it'll contain the
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// result of the read that happened just before debugint was set.
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add_dbus_scan(target, &field[scan], out + 8*scan, NULL, DBUS_OP_READ,
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address, DMCONTROL_HALTNOT);
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scan++;
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// This scan contains the results of the read the caller requested, as well
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// as an interrupt bit worth looking at.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan, DBUS_OP_READ,
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address, DMCONTROL_HALTNOT);
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scan++;
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// This scan contains the results of the read the caller requested, as
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// well as an interrupt bit worth looking at.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_READ, address, DMCONTROL_HALTNOT);
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scan++;
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}
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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@ -697,25 +701,28 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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} else {
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cache_clean(target);
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int interrupt = buf_get_u32(in + 8*(scan-1), DBUS_DATA_START + 33, 1);
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if (interrupt) {
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increase_interrupt_high_delay(target);
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// Slow path wait for it to clear.
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if (wait_for_debugint_clear(target, false) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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dump_debug_ram(target);
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return ERROR_FAIL;
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if (run || address < CACHE_NO_READ) {
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int interrupt = buf_get_u32(in + 8*(scan-1), DBUS_DATA_START + 33, 1);
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if (interrupt) {
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increase_interrupt_high_delay(target);
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// Slow path wait for it to clear.
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if (wait_for_debugint_clear(target, false) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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dump_debug_ram(target);
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return ERROR_FAIL;
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}
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} else {
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// We read a useful value in that last scan.
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unsigned int read_addr = buf_get_u32(in + 8*(scan-1),
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DBUS_ADDRESS_START, info->addrbits);
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if (read_addr != address) {
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LOG_INFO("Got data from 0x%x but expected it from 0x%x",
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read_addr, address);
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}
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info->dram_cache[read_addr].data =
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buf_get_u64(in + 8*(scan-1), DBUS_DATA_START, DBUS_DATA_SIZE);
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info->dram_cache[read_addr].valid = true;
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}
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} else {
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// We read a useful value in that last scan.
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unsigned int read_addr = buf_get_u32(in + 8*(scan-1), DBUS_ADDRESS_START, info->addrbits);
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if (read_addr != address) {
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LOG_INFO("Got data from 0x%x but expected it from 0x%x",
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read_addr, address);
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}
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info->dram_cache[read_addr].data =
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buf_get_u64(in + 8*(scan-1), DBUS_DATA_START, DBUS_DATA_SIZE);
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info->dram_cache[read_addr].valid = true;
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}
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}
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@ -747,7 +754,8 @@ uint64_t cache_get(struct target *target, slot_t slot)
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/* Write instruction that jumps from the specified word in Debug RAM to resume
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* in Debug ROM. */
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static void dram_write_jump(struct target *target, unsigned int index, bool set_interrupt)
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static void dram_write_jump(struct target *target, unsigned int index,
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bool set_interrupt)
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{
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dram_write32(target, index,
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jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
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@ -1614,7 +1622,7 @@ static int riscv_read_memory(struct target *target, uint32_t address,
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return ERROR_FAIL;
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}
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cache_set_jump(target, 3);
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cache_write(target, 4, false);
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cache_write(target, CACHE_NO_READ, false);
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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const int max_batch_size = 256;
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