zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Cortex-A/R: Add missing timeout for loop polling DSCR & fix timeout types 

Change-Id: I345658cfdc8a34a98418727423ac6bd562e980f3
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/3201
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
__archive__
Evan Hunter 2016-01-12 18:13:27 +00:00 committed by Andreas Fritiofson
parent f0682623ca
commit 4fef1d5bb0
1 changed files with 14 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/target/cortex_a.c
View File

@ -299,7 +299,7 @@ static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool f
* Writes final value of DSCR into *dscr. Pass force to force always * Writes final value of DSCR into *dscr. Pass force to force always
* reading DSCR at least once. */ * reading DSCR at least once. */
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
long long then = timeval_ms(); int64_t then = timeval_ms();
while ((*dscr & DSCR_INSTR_COMP) == 0 || force) { while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
force = false; force = false;
int retval = mem_ap_read_atomic_u32(armv7a->debug_ap, int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
@ -342,7 +342,7 @@ static int cortex_a_exec_opcode(struct target *target,
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
long long then = timeval_ms(); int64_t then = timeval_ms();
do { do {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap, retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
@ -431,7 +431,7 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
} }
/* Wait for DTRRXfull then read DTRRTX */ /* Wait for DTRRXfull then read DTRRTX */
long long then = timeval_ms(); int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) { while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap, retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
@ -574,7 +574,7 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
dscr = *dscr_p; dscr = *dscr_p;
/* Wait for DTRRXfull */ /* Wait for DTRRXfull */
long long then = timeval_ms(); int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) { while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap, retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR, a->armv7a_common.debug_base + CPUDBG_DSCR,
@ -606,7 +606,7 @@ static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
int retval; int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */ /* set up invariant: INSTR_COMP is set after ever DPM operation */
long long then = timeval_ms(); int64_t then = timeval_ms();
for (;; ) { for (;; ) {
retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap, retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR, a->armv7a_common.debug_base + CPUDBG_DSCR,
@ -974,7 +974,7 @@ static int cortex_a_halt(struct target *target)
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
long long then = timeval_ms(); int64_t then = timeval_ms();
for (;; ) { for (;; ) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap, retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
@ -1121,7 +1121,7 @@ static int cortex_a_internal_restart(struct target *target)
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
long long then = timeval_ms(); int64_t then = timeval_ms();
for (;; ) { for (;; ) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap, retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
@ -1443,7 +1443,7 @@ static int cortex_a_step(struct target *target, int current, uint32_t address,
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
long long then = timeval_ms(); int64_t then = timeval_ms();
while (target->state != TARGET_HALTED) { while (target->state != TARGET_HALTED) {
retval = cortex_a_poll(target); retval = cortex_a_poll(target);
if (retval != ERROR_OK) if (retval != ERROR_OK)
@ -1977,7 +1977,7 @@ static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
{ {
/* Waits until the specified bit(s) of DSCR take on a specified value. */ /* Waits until the specified bit(s) of DSCR take on a specified value. */
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
long long then = timeval_ms(); int64_t then = timeval_ms();
int retval; int retval;
while ((*dscr & mask) != value) { while ((*dscr & mask) != value) {
@ -2908,6 +2908,7 @@ static int cortex_a_handle_target_request(void *priv)
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
/* check if we have data */ /* check if we have data */
int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) { while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap, retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &request); armv7a->debug_base + CPUDBG_DTRTX, &request);
@ -2916,6 +2917,10 @@ static int cortex_a_handle_target_request(void *priv)
retval = mem_ap_read_atomic_u32(armv7a->debug_ap, retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
} }
if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for dtr tx full");
return ERROR_FAIL;
}
} }
} }