Flash handling for STM32F76x/77x and F446 added
- added ids for various parts - rewrite of sector allocation to deal with dual-bank F76x/77x - single- / dual-bank mode for F76x/77x - sector protection adapted for F76x/77x in dual-bank mode - handling of additional option bits (28-31) in FLASH_OPTCR in options_read and options_write for F42x/43x/469/479/7xx, options bits 0-1 masked out - check for sensible value of user_options in options_write - some #defines clarified, non-needed ones removed - docs updated (options read, options write) Change-Id: Ie4db80e60baa7d2663e024ab1f278640b1ce901b Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/3526 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>__archive__
Andreas Bolsch
Andreas Fritiofson
parent
f4dfa3b0d0
commit
4e9ee81f0c
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@ -5827,8 +5827,8 @@ The @var{num} parameter is a value shown by @command{flash banks}.
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@end deffn
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@deffn {Flash Driver} stm32f2x
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All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics
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include internal flash and use ARM Cortex-M3/M4 cores.
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All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from ST Microelectronics
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include internal flash and use ARM Cortex-M3/M4/M7 cores.
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The driver automatically recognizes a number of these chips using
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the chip identification register, and autoconfigures itself.
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@ -5851,6 +5851,19 @@ The @var{num} parameter is a value shown by @command{flash banks}.
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Unlocks the entire stm32 device.
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The @var{num} parameter is a value shown by @command{flash banks}.
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@end deffn
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@deffn Command {stm32f2x options_read} num
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Reads and displays user options and (where implemented) boot_addr0 and boot_addr1.
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The @var{num} parameter is a value shown by @command{flash banks}.
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@end deffn
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@deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
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Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
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Warning: The meaning of the various bits depends on the device, always check datasheet!
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The @var{num} parameter is a value shown by @command{flash banks}, user_options a
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12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, boot_addr0 and boot_addr1
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two halfwords (of FLASH_OPTCR1).
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@end deffn
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@end deffn
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@deffn {Flash Driver} stm32lx
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@ -63,9 +63,15 @@
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* 1 MiByte STM32F42x/43x part with DB1M Option set:
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* 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
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*
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* STM32F7
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* STM32F7[4|5]
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* 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
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*
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* STM32F7[6|7]
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* 1 MiByte part in single bank mode with 4 x 32, 1 x 128, 3 x 256.
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* 1 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 3 x 128 each.
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* 2 MiByte part in single-bank mode with 4 x 32, 1 x 128, 7 x 256.
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* 2 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 7 x 128 each.
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*
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* Protection size is sector size.
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*
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* Tested with STM3220F-EVAL board.
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@ -84,6 +90,9 @@
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* RM0385
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* http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
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*
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* RM0410
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* http://www.st.com/resource/en/reference_manual/dm00224583.pdf
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*
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* STM32F1x series - notice that this code was copy, pasted and knocked
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* into a stm32f2x driver, so in case something has been converted or
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* bugs haven't been fixed, here are the original manuals:
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@ -111,11 +120,10 @@
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#define STM32_FLASH_OPTCR1 0x40023c18
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/* FLASH_CR register bits */
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#define FLASH_PG (1 << 0)
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#define FLASH_SER (1 << 1)
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#define FLASH_MER (1 << 2)
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#define FLASH_MER1 (1 << 15)
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#define FLASH_MER (1 << 2) /* MER/MER1 for f76x/77x */
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#define FLASH_MER1 (1 << 15) /* MER2 for f76x/77x, confusing ... */
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#define FLASH_STRT (1 << 16)
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#define FLASH_PSIZE_8 (0 << 8)
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#define FLASH_PSIZE_16 (1 << 8)
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@ -127,7 +135,6 @@
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#define FLASH_LOCK (1 << 31)
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/* FLASH_SR register bits */
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#define FLASH_BSY (1 << 16)
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#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
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#define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
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@ -138,22 +145,12 @@
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#define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
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/* STM32_FLASH_OPTCR register bits */
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#define OPT_LOCK (1 << 0)
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#define OPT_START (1 << 1)
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/* STM32_FLASH_OBR bit definitions (reading) */
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#define OPT_ERROR 0
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#define OPT_READOUT 1
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#define OPT_RDWDGSW 2
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#define OPT_RDRSTSTOP 3
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#define OPT_RDRSTSTDBY 4
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#define OPT_BFB2 5 /* dual flash bank only */
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#define OPT_DB1M 14 /* 1 MiB devices dual flash bank option */
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#define OPTCR_LOCK (1 << 0)
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#define OPTCR_START (1 << 1)
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#define OPTCR_NDBANK (1 << 29) /* not dual bank mode */
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#define OPTCR_DB1M (1 << 30) /* 1 MiB devices dual flash bank option */
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/* register unlock keys */
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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@ -163,14 +160,17 @@
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struct stm32x_options {
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uint8_t RDP;
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uint8_t user_options;
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uint16_t user_options; /* bit 0-7 usual options, bit 8-11 extra options */
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uint32_t protection;
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uint32_t boot_addr;
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};
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struct stm32x_flash_bank {
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struct stm32x_options option_bytes;
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int probed;
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bool has_large_mem; /* stm32f42x/stm32f43x family */
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bool has_large_mem; /* F42x/43x/469/479/7xx in dual bank mode */
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bool has_boot_addr; /* F7xx */
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bool has_extra_options; /* F42x/43x/469/479/7xx */
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uint32_t user_bank_size;
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};
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@ -284,7 +284,7 @@ static int stm32x_unlock_option_reg(struct target *target)
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if (retval != ERROR_OK)
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return retval;
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if ((ctrl & OPT_LOCK) == 0)
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if ((ctrl & OPTCR_LOCK) == 0)
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return ERROR_OK;
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/* unlock option registers */
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@ -300,7 +300,7 @@ static int stm32x_unlock_option_reg(struct target *target)
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if (retval != ERROR_OK)
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return retval;
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if (ctrl & OPT_LOCK) {
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if (ctrl & OPTCR_LOCK) {
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LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
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return ERROR_TARGET_FAILURE;
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}
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@ -321,19 +321,31 @@ static int stm32x_read_options(struct flash_bank *bank)
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if (retval != ERROR_OK)
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return retval;
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stm32x_info->option_bytes.user_options = optiondata & 0xec;
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/* caution: F2 implements 5 bits (WDG_SW only)
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* whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
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stm32x_info->option_bytes.user_options = optiondata & 0xfc;
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stm32x_info->option_bytes.RDP = (optiondata >> 8) & 0xff;
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stm32x_info->option_bytes.protection = (optiondata >> 16) & 0xfff;
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if (stm32x_info->has_large_mem) {
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if (stm32x_info->has_extra_options) {
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/* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
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stm32x_info->option_bytes.user_options |= (optiondata >> 20) & 0xf00;
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}
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if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
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retval = target_read_u32(target, STM32_FLASH_OPTCR1, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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/* append protection bits */
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/* FLASH_OPTCR1 has quite diffent meanings ... */
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if (stm32x_info->has_boot_addr) {
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/* for F7xx it contains boot0 and boot1 */
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stm32x_info->option_bytes.boot_addr = optiondata;
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} else {
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/* for F42x/43x/469/479 it contains 12 additional protection bits */
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stm32x_info->option_bytes.protection |= (optiondata >> 4) & 0x00fff000;
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}
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}
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if (stm32x_info->option_bytes.RDP != 0xAA)
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LOG_INFO("Device Security Bit Set");
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@ -345,7 +357,7 @@ static int stm32x_write_options(struct flash_bank *bank)
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{
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struct stm32x_flash_bank *stm32x_info = NULL;
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struct target *target = bank->target;
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uint32_t optiondata;
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uint32_t optiondata, optiondata2;
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stm32x_info = bank->driver_priv;
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@ -354,26 +366,36 @@ static int stm32x_write_options(struct flash_bank *bank)
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return retval;
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/* rebuild option data */
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optiondata = stm32x_info->option_bytes.user_options;
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optiondata = stm32x_info->option_bytes.user_options & 0xfc;
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optiondata |= stm32x_info->option_bytes.RDP << 8;
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optiondata |= (stm32x_info->option_bytes.protection & 0x0fff) << 16;
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if (stm32x_info->has_extra_options) {
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/* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
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optiondata |= (stm32x_info->option_bytes.user_options & 0xf00) << 20;
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}
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if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
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if (stm32x_info->has_boot_addr) {
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/* F7xx uses FLASH_OPTCR1 for boot0 and boot1 ... */
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optiondata2 = stm32x_info->option_bytes.boot_addr;
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} else {
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/* F42x/43x/469/479 uses FLASH_OPTCR1 for additional protection bits */
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optiondata2 = (stm32x_info->option_bytes.protection & 0x00fff000) << 4;
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}
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retval = target_write_u32(target, STM32_FLASH_OPTCR1, optiondata2);
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if (retval != ERROR_OK)
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return retval;
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}
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/* program options */
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retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata);
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if (retval != ERROR_OK)
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return retval;
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if (stm32x_info->has_large_mem) {
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uint32_t optiondata2 = 0;
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optiondata2 |= (stm32x_info->option_bytes.protection & 0x00fff000) << 4;
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retval = target_write_u32(target, STM32_FLASH_OPTCR1, optiondata2);
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if (retval != ERROR_OK)
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return retval;
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}
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/* start programming cycle */
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retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPT_START);
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retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_START);
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if (retval != ERROR_OK)
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return retval;
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@ -383,7 +405,7 @@ static int stm32x_write_options(struct flash_bank *bank)
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return retval;
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/* relock registers */
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retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPT_LOCK);
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retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_LOCK);
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if (retval != ERROR_OK)
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return retval;
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@ -401,12 +423,26 @@ static int stm32x_protect_check(struct flash_bank *bank)
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return retval;
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}
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if (stm32x_info->has_boot_addr && stm32x_info->has_large_mem) {
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/* F76x/77x: bit k protects sectors 2*k and 2*k+1 */
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for (int i = 0; i < (bank->num_sectors >> 1); i++) {
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if (stm32x_info->option_bytes.protection & (1 << i)) {
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bank->sectors[i << 1].is_protected = 0;
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bank->sectors[(i << 1) + 1].is_protected = 0;
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} else {
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bank->sectors[i << 1].is_protected = 1;
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bank->sectors[(i << 1) + 1].is_protected = 1;
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}
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}
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} else {
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/* one protection bit per sector */
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for (int i = 0; i < bank->num_sectors; i++) {
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if (stm32x_info->option_bytes.protection & (1 << i))
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bank->sectors[i].is_protected = 0;
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else
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bank->sectors[i].is_protected = 1;
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}
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}
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return ERROR_OK;
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}
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@ -416,8 +452,7 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
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struct target *target = bank->target;
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int i;
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assert(first < bank->num_sectors);
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assert(last < bank->num_sectors);
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assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
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if (bank->target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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@ -477,8 +512,18 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
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return retval;
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}
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for (int i = first; i <= last; i++) {
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if (stm32x_info->has_boot_addr && stm32x_info->has_large_mem) {
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/* F76x/77x: bit k protects sectors 2*k and 2*k+1 */
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if ((first & 1) != 0 || (last & 1) != 1) {
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LOG_ERROR("sector protection must be double sector aligned");
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return ERROR_FAIL;
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} else {
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first >>= 1;
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last >>= 1;
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}
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}
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for (int i = first; i <= last; i++) {
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if (set)
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stm32x_info->option_bytes.protection &= ~(1 << i);
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else
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@ -719,14 +764,31 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
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return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
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}
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static void setup_sector(struct flash_bank *bank, int start, int num, int size)
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static int setup_sector(struct flash_bank *bank, int start, int num, int size)
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{
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for (int i = start; i < (start + num) ; i++) {
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assert(i < bank->num_sectors);
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bank->sectors[i].offset = bank->size;
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bank->sectors[i].size = size;
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bank->size += bank->sectors[i].size;
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LOG_DEBUG("sector %d: %dkBytes", i, size >> 10);
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}
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return start + num;
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}
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static void setup_bank(struct flash_bank *bank, int start,
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uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
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{
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int remain;
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start = setup_sector(bank, start, 4, (max_sector_size_in_kb / 8) * 1024);
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start = setup_sector(bank, start, 1, (max_sector_size_in_kb / 2) * 1024);
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/* remaining sectors all of size max_sector_size_in_kb */
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remain = (flash_size_in_kb / max_sector_size_in_kb) - 1;
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start = setup_sector(bank, start, remain, max_sector_size_in_kb * 1024);
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}
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static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
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@ -774,6 +836,8 @@ static int stm32x_probe(struct flash_bank *bank)
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stm32x_info->probed = 0;
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stm32x_info->has_large_mem = false;
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stm32x_info->has_boot_addr = false;
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stm32x_info->has_extra_options = false;
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/* read stm32 device id register */
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int retval = stm32x_get_device_id(bank, &device_id);
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@ -781,33 +845,50 @@ static int stm32x_probe(struct flash_bank *bank)
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return retval;
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LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
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/* set max flash size depending on family */
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/* set max flash size depending on family, id taken from AN2606 */
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switch (device_id & 0xfff) {
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case 0x411:
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case 0x413:
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case 0x441:
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case 0x411: /* F20x/21x */
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case 0x413: /* F40x/41x */
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max_flash_size_in_kb = 1024;
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break;
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case 0x419:
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case 0x434:
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case 0x419: /* F42x/43x */
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case 0x434: /* F469/479 */
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stm32x_info->has_extra_options = true;
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max_flash_size_in_kb = 2048;
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break;
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case 0x423:
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case 0x423: /* F401xB/C */
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max_flash_size_in_kb = 256;
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break;
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case 0x431:
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case 0x433:
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case 0x421:
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case 0x421: /* F446 */
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case 0x431: /* F411 */
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case 0x433: /* F401xD/E */
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case 0x441: /* F412 */
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max_flash_size_in_kb = 512;
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break;
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case 0x458:
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case 0x458: /* F410 */
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max_flash_size_in_kb = 128;
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break;
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case 0x449:
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case 0x449: /* F74x/75x */
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max_flash_size_in_kb = 1024;
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max_sector_size_in_kb = 256;
|
||||
flash_size_reg = 0x1FF0F442;
|
||||
stm32x_info->has_extra_options = true;
|
||||
stm32x_info->has_boot_addr = true;
|
||||
break;
|
||||
|
||||
case 0x451: /* F76x/77x */
|
||||
max_flash_size_in_kb = 2048;
|
||||
max_sector_size_in_kb = 256;
|
||||
flash_size_reg = 0x1FF0F442;
|
||||
stm32x_info->has_extra_options = true;
|
||||
stm32x_info->has_boot_addr = true;
|
||||
break;
|
||||
|
||||
default:
|
||||
LOG_WARNING("Cannot identify target as a STM32 family.");
|
||||
return ERROR_FAIL;
|
||||
|
|
@ -836,33 +917,48 @@ static int stm32x_probe(struct flash_bank *bank)
|
|||
/* did we assign flash size? */
|
||||
assert(flash_size_in_kb != 0xffff);
|
||||
|
||||
/* calculate numbers of pages */
|
||||
int num_pages = (flash_size_in_kb / max_sector_size_in_kb) + 4;
|
||||
|
||||
/* Devices with > 1024 kiByte always are dual-banked */
|
||||
if (flash_size_in_kb > 1024)
|
||||
stm32x_info->has_large_mem = true;
|
||||
|
||||
/* F42x/43x 1024 kiByte devices have a dual bank option */
|
||||
if ((device_id & 0xfff) == 0x419 && (flash_size_in_kb == 1024)) {
|
||||
/* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
|
||||
if ((device_id & 0xfff) == 0x419 || (device_id & 0xfff) == 0x434) {
|
||||
uint32_t optiondata;
|
||||
retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_DEBUG("unable to read option bytes");
|
||||
return retval;
|
||||
}
|
||||
if (optiondata & (1 << OPT_DB1M)) {
|
||||
if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) {
|
||||
stm32x_info->has_large_mem = true;
|
||||
LOG_INFO("Dual Bank 1024 kiB STM32F42x/43x found");
|
||||
LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
|
||||
} else {
|
||||
stm32x_info->has_large_mem = false;
|
||||
LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
|
||||
}
|
||||
}
|
||||
|
||||
/* check for dual-banked devices */
|
||||
if (stm32x_info->has_large_mem)
|
||||
num_pages += 4;
|
||||
/* F76x/77x devices have a dual bank option */
|
||||
if ((device_id & 0xfff) == 0x451) {
|
||||
uint32_t optiondata;
|
||||
retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_DEBUG("unable to read option bytes");
|
||||
return retval;
|
||||
}
|
||||
if (optiondata & OPTCR_NDBANK) {
|
||||
stm32x_info->has_large_mem = false;
|
||||
LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
|
||||
} else {
|
||||
stm32x_info->has_large_mem = true;
|
||||
max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */
|
||||
LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
|
||||
}
|
||||
}
|
||||
|
||||
/* check that calculation result makes sense */
|
||||
assert(num_pages > 0);
|
||||
/* calculate numbers of pages */
|
||||
int num_pages = flash_size_in_kb / max_sector_size_in_kb
|
||||
+ (stm32x_info->has_large_mem ? 8 : 4);
|
||||
|
||||
if (bank->sectors) {
|
||||
free(bank->sectors);
|
||||
|
|
@ -872,35 +968,25 @@ static int stm32x_probe(struct flash_bank *bank)
|
|||
bank->base = base_address;
|
||||
bank->num_sectors = num_pages;
|
||||
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
|
||||
bank->size = 0;
|
||||
|
||||
/* fixed memory */
|
||||
setup_sector(bank, 0, 4, (max_sector_size_in_kb / 8) * 1024);
|
||||
setup_sector(bank, 4, 1, (max_sector_size_in_kb / 2) * 1024);
|
||||
|
||||
if (stm32x_info->has_large_mem) {
|
||||
if (flash_size_in_kb == 1024) {
|
||||
setup_sector(bank, 5, 3, 128 * 1024);
|
||||
setup_sector(bank, 12, 4, 16 * 1024);
|
||||
setup_sector(bank, 16, 1, 64 * 1024);
|
||||
setup_sector(bank, 17, 3, 128 * 1024);
|
||||
} else {
|
||||
setup_sector(bank, 5, 7, 128 * 1024);
|
||||
setup_sector(bank, 12, 4, 16 * 1024);
|
||||
setup_sector(bank, 16, 1, 64 * 1024);
|
||||
setup_sector(bank, 17, 7, 128 * 1024);
|
||||
}
|
||||
} else {
|
||||
setup_sector(bank, 4 + 1, MIN(12, num_pages) - 5,
|
||||
max_sector_size_in_kb * 1024);
|
||||
}
|
||||
for (i = 0; i < num_pages; i++) {
|
||||
bank->sectors[i].is_erased = -1;
|
||||
bank->sectors[i].is_protected = 0;
|
||||
}
|
||||
bank->size = 0;
|
||||
LOG_DEBUG("allocated %d sectors", num_pages);
|
||||
|
||||
if (stm32x_info->has_large_mem) {
|
||||
/* dual-bank */
|
||||
setup_bank(bank, 0, flash_size_in_kb >> 1, max_sector_size_in_kb);
|
||||
setup_bank(bank, num_pages >> 1, flash_size_in_kb >> 1,
|
||||
max_sector_size_in_kb);
|
||||
} else {
|
||||
/* single-bank */
|
||||
setup_bank(bank, 0, flash_size_in_kb, max_sector_size_in_kb);
|
||||
}
|
||||
assert((bank->size >> 10) == flash_size_in_kb);
|
||||
|
||||
stm32x_info->probed = 1;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -950,11 +1036,24 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
|
|||
case 0x2003:
|
||||
rev_str = "X";
|
||||
break;
|
||||
|
||||
case 0x2007:
|
||||
rev_str = "1";
|
||||
break;
|
||||
|
||||
case 0x200F:
|
||||
rev_str = "V";
|
||||
break;
|
||||
|
||||
case 0x201F:
|
||||
rev_str = "2";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x413:
|
||||
case 0x419:
|
||||
case 0x434:
|
||||
device_str = "STM32F4xx";
|
||||
|
||||
switch (rev_id) {
|
||||
|
|
@ -979,6 +1078,7 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x421:
|
||||
device_str = "STM32F446";
|
||||
|
||||
|
|
@ -988,6 +1088,7 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x423:
|
||||
case 0x431:
|
||||
case 0x433:
|
||||
|
|
@ -1019,8 +1120,9 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case 0x434:
|
||||
device_str = "STM32F46x/F47x";
|
||||
|
||||
case 0x451:
|
||||
device_str = "STM32F7[6|7]x";
|
||||
|
||||
switch (rev_id) {
|
||||
case 0x1000:
|
||||
|
|
@ -1146,6 +1248,7 @@ static int stm32x_mass_erase(struct flash_bank *bank)
|
|||
flash_mer = FLASH_MER | FLASH_MER1;
|
||||
else
|
||||
flash_mer = FLASH_MER;
|
||||
|
||||
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), flash_mer);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
|
@ -1193,6 +1296,107 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
|
|||
return retval;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(stm32f2x_handle_options_read_command)
|
||||
{
|
||||
int retval;
|
||||
struct flash_bank *bank;
|
||||
struct stm32x_flash_bank *stm32x_info = NULL;
|
||||
|
||||
if (CMD_ARGC != 1) {
|
||||
command_print(CMD_CTX, "stm32f2x options_read <bank>");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
retval = stm32x_read_options(bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
stm32x_info = bank->driver_priv;
|
||||
if (stm32x_info->has_extra_options) {
|
||||
if (stm32x_info->has_boot_addr) {
|
||||
uint32_t boot_addr = stm32x_info->option_bytes.boot_addr;
|
||||
|
||||
command_print(CMD_CTX, "stm32f2x user_options 0x%03X,"
|
||||
" boot_add0 0x%04X, boot_add1 0x%04X",
|
||||
stm32x_info->option_bytes.user_options,
|
||||
boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
|
||||
} else {
|
||||
command_print(CMD_CTX, "stm32f2x user_options 0x%03X,",
|
||||
stm32x_info->option_bytes.user_options);
|
||||
}
|
||||
} else {
|
||||
command_print(CMD_CTX, "stm32f2x user_options 0x%02X",
|
||||
stm32x_info->option_bytes.user_options);
|
||||
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(stm32f2x_handle_options_write_command)
|
||||
{
|
||||
int retval;
|
||||
struct flash_bank *bank;
|
||||
struct stm32x_flash_bank *stm32x_info = NULL;
|
||||
uint16_t user_options, boot_addr0, boot_addr1;
|
||||
|
||||
if (CMD_ARGC < 1) {
|
||||
command_print(CMD_CTX, "stm32f2x options_write <bank> ...");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
retval = stm32x_read_options(bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
stm32x_info = bank->driver_priv;
|
||||
if (stm32x_info->has_boot_addr) {
|
||||
if (CMD_ARGC != 4) {
|
||||
command_print(CMD_CTX, "stm32f2x options_write <bank> <user_options>"
|
||||
" <boot_addr0> <boot_addr1>");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[2], boot_addr0);
|
||||
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], boot_addr1);
|
||||
stm32x_info->option_bytes.boot_addr = boot_addr0 | (((uint32_t) boot_addr1) << 16);
|
||||
} else {
|
||||
if (CMD_ARGC != 2) {
|
||||
command_print(CMD_CTX, "stm32f2x options_write <bank> <user_options>");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], user_options);
|
||||
if (user_options & (stm32x_info->has_extra_options ? ~0xffc : ~0xfc)) {
|
||||
command_print(CMD_CTX, "stm32f2x invalid user_options");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
stm32x_info->option_bytes.user_options = user_options;
|
||||
|
||||
if (stm32x_write_options(bank) != ERROR_OK) {
|
||||
command_print(CMD_CTX, "stm32f2x failed to write options");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* switching between single- and dual-bank modes requires re-probe */
|
||||
/* ... and reprogramming of whole flash */
|
||||
stm32x_info->probed = 0;
|
||||
|
||||
command_print(CMD_CTX, "stm32f2x write options complete.\n"
|
||||
"INFO: a reset or power cycle is required "
|
||||
"for the new settings to take effect.");
|
||||
return retval;
|
||||
}
|
||||
|
||||
static const struct command_registration stm32x_exec_command_handlers[] = {
|
||||
{
|
||||
.name = "lock",
|
||||
|
|
@ -1215,6 +1419,20 @@ static const struct command_registration stm32x_exec_command_handlers[] = {
|
|||
.usage = "bank_id",
|
||||
.help = "Erase entire flash device.",
|
||||
},
|
||||
{
|
||||
.name = "options_read",
|
||||
.handler = stm32f2x_handle_options_read_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.usage = "bank_id",
|
||||
.help = "Read and display device option bytes.",
|
||||
},
|
||||
{
|
||||
.name = "options_write",
|
||||
.handler = stm32f2x_handle_options_write_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.usage = "bank_id user_options [ boot_add0 boot_add1]",
|
||||
.help = "Write option bytes",
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue