ARM926: remove exports and forward decls
Unneeded exports cause confusion about the module interfaces. Only the Feroceon code builds on this, so only routines it reuses should be public.. Make most remaining functions static, and fix some of the line-too-long issues. The forward decls are just code clutter; move their references later, after the normal declarations. Turns out we don't need even one forward declaration in this file. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
053a763aa6
commit
4d17541a2c
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@ -33,94 +33,8 @@
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#define _DEBUG_INSTRUCTION_EXECUTION_
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#endif
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/* cli handling */
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int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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/* forward declarations */
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int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
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int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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int arm926ejs_quit(void);
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int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
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static int arm926ejs_mmu(struct target_s *target, int *enabled);
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int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
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int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
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static int arm926ejs_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
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{
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if (cpnum!=15)
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{
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
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}
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static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
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{
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if (cpnum!=15)
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{
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
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}
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target_type_t arm926ejs_target =
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{
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.name = "arm926ejs",
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.poll = arm7_9_poll,
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.arch_state = arm926ejs_arch_state,
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.target_request_data = arm7_9_target_request_data,
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.halt = arm7_9_halt,
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.resume = arm7_9_resume,
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.step = arm7_9_step,
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.assert_reset = arm7_9_assert_reset,
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.deassert_reset = arm7_9_deassert_reset,
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.soft_reset_halt = arm926ejs_soft_reset_halt,
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.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
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.read_memory = arm7_9_read_memory,
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.write_memory = arm926ejs_write_memory,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.checksum_memory = arm7_9_checksum_memory,
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.blank_check_memory = arm7_9_blank_check_memory,
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.run_algorithm = armv4_5_run_algorithm,
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.add_breakpoint = arm7_9_add_breakpoint,
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.remove_breakpoint = arm7_9_remove_breakpoint,
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.add_watchpoint = arm7_9_add_watchpoint,
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.remove_watchpoint = arm7_9_remove_watchpoint,
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.register_commands = arm926ejs_register_commands,
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.target_create = arm926ejs_target_create,
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.init_target = arm926ejs_init_target,
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.examine = arm9tdmi_examine,
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.quit = arm926ejs_quit,
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.virt2phys = arm926ejs_virt2phys,
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.mmu = arm926ejs_mmu,
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.read_phys_memory = arm926ejs_read_phys_memory,
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.write_phys_memory = arm926ejs_write_phys_memory,
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.mrc = arm926ejs_mrc,
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.mcr = arm926ejs_mcr,
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};
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int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field)
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static int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv,
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scan_field_t *field)
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{
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/* FIX!!!! this code should be reenabled. For now it does not check
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* the queue...*/
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@ -144,7 +58,8 @@ int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *f
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#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
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int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
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static int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm, uint32_t *value)
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{
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int retval = ERROR_OK;
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armv4_5_common_t *armv4_5 = target->arch_info;
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@ -226,7 +141,18 @@ int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
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return ERROR_OK;
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}
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int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
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static int arm926ejs_mrc(target_t *target, int cpnum, uint32_t op1,
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uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
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{
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if (cpnum != 15) {
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
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}
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static int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm, uint32_t value)
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{
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int retval = ERROR_OK;
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armv4_5_common_t *armv4_5 = target->arch_info;
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@ -306,6 +232,16 @@ int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t
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return ERROR_OK;
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}
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static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1,
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uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
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{
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if (cpnum != 15) {
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
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}
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static int arm926ejs_examine_debug_reason(target_t *target)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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@ -410,7 +346,7 @@ static int arm926ejs_examine_debug_reason(target_t *target)
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return ERROR_OK;
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}
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uint32_t arm926ejs_get_ttb(target_t *target)
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static uint32_t arm926ejs_get_ttb(target_t *target)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -425,7 +361,8 @@ uint32_t arm926ejs_get_ttb(target_t *target)
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return ttb;
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}
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void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
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static void arm926ejs_disable_mmu_caches(target_t *target, int mmu,
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int d_u_cache, int i_cache)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -476,7 +413,8 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int
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arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
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}
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void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
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static void arm926ejs_enable_mmu_caches(target_t *target, int mmu,
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int d_u_cache, int i_cache)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -500,7 +438,7 @@ void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i
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arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
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}
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void arm926ejs_post_debug_entry(target_t *target)
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static void arm926ejs_post_debug_entry(target_t *target)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -542,7 +480,7 @@ void arm926ejs_post_debug_entry(target_t *target)
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arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
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}
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void arm926ejs_pre_restore_context(target_t *target)
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static void arm926ejs_pre_restore_context(target_t *target)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -563,7 +501,11 @@ void arm926ejs_pre_restore_context(target_t *target)
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arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
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}
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int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
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static int arm926ejs_get_arch_pointers(target_t *target,
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armv4_5_common_t **armv4_5_p,
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arm7_9_common_t **arm7_9_p,
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arm9tdmi_common_t **arm9tdmi_p,
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arm926ejs_common_t **arm926ejs_p)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9;
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@ -702,7 +644,8 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
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return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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}
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int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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int arm926ejs_write_memory(struct target_s *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int retval;
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armv4_5_common_t *armv4_5 = target->arch_info;
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@ -765,7 +708,9 @@ int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t s
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return retval;
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}
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int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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static int arm926ejs_write_phys_memory(struct target_s *target,
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uint32_t address, uint32_t size,
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uint32_t count, uint8_t *buffer)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -775,7 +720,9 @@ int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint3
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return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer);
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}
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int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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static int arm926ejs_read_phys_memory(struct target_s *target,
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uint32_t address, uint32_t size,
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uint32_t count, uint8_t *buffer)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -785,19 +732,21 @@ int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32
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return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer);
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}
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int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
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static int arm926ejs_init_target(struct command_context_s *cmd_ctx,
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struct target_s *target)
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{
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arm9tdmi_init_target(cmd_ctx, target);
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return ERROR_OK;
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}
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int arm926ejs_quit(void)
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static int arm926ejs_quit(void)
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{
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return ERROR_OK;
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}
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int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
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int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs,
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jtag_tap_t *tap)
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{
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arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
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arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
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@ -834,7 +783,7 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jt
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return ERROR_OK;
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}
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int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
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static int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
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{
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arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
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@ -843,24 +792,8 @@ int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
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return ERROR_OK;
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}
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int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
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{
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int retval;
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command_t *arm926ejs_cmd;
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retval = arm9tdmi_register_commands(cmd_ctx);
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arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
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register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
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register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
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return retval;
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}
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int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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static int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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int retval;
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target_t *target = get_current_target(cmd_ctx);
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@ -925,7 +858,9 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd,
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return ERROR_OK;
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}
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int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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static int
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arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5;
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@ -981,3 +916,73 @@ static int arm926ejs_mmu(struct target_s *target, int *enabled)
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*enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
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return ERROR_OK;
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}
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int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
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{
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int retval;
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command_t *arm926ejs_cmd;
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retval = arm9tdmi_register_commands(cmd_ctx);
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arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs",
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NULL, COMMAND_ANY,
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"arm926ejs specific commands");
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register_command(cmd_ctx, arm926ejs_cmd, "cp15",
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arm926ejs_handle_cp15_command, COMMAND_EXEC,
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"display/modify cp15 register "
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"<opcode_1> <opcode_2> <CRn> <CRm> [value]");
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register_command(cmd_ctx, arm926ejs_cmd, "cache_info",
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arm926ejs_handle_cache_info_command, COMMAND_EXEC,
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"display information about target caches");
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return retval;
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}
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target_type_t arm926ejs_target =
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{
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.name = "arm926ejs",
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.poll = arm7_9_poll,
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.arch_state = arm926ejs_arch_state,
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||||
|
||||
.target_request_data = arm7_9_target_request_data,
|
||||
|
||||
.halt = arm7_9_halt,
|
||||
.resume = arm7_9_resume,
|
||||
.step = arm7_9_step,
|
||||
|
||||
.assert_reset = arm7_9_assert_reset,
|
||||
.deassert_reset = arm7_9_deassert_reset,
|
||||
.soft_reset_halt = arm926ejs_soft_reset_halt,
|
||||
|
||||
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
|
||||
|
||||
.read_memory = arm7_9_read_memory,
|
||||
.write_memory = arm926ejs_write_memory,
|
||||
.bulk_write_memory = arm7_9_bulk_write_memory,
|
||||
.checksum_memory = arm7_9_checksum_memory,
|
||||
.blank_check_memory = arm7_9_blank_check_memory,
|
||||
|
||||
.run_algorithm = armv4_5_run_algorithm,
|
||||
|
||||
.add_breakpoint = arm7_9_add_breakpoint,
|
||||
.remove_breakpoint = arm7_9_remove_breakpoint,
|
||||
.add_watchpoint = arm7_9_add_watchpoint,
|
||||
.remove_watchpoint = arm7_9_remove_watchpoint,
|
||||
|
||||
.register_commands = arm926ejs_register_commands,
|
||||
.target_create = arm926ejs_target_create,
|
||||
.init_target = arm926ejs_init_target,
|
||||
.examine = arm9tdmi_examine,
|
||||
.quit = arm926ejs_quit,
|
||||
.virt2phys = arm926ejs_virt2phys,
|
||||
.mmu = arm926ejs_mmu,
|
||||
|
||||
.read_phys_memory = arm926ejs_read_phys_memory,
|
||||
.write_phys_memory = arm926ejs_write_phys_memory,
|
||||
.mrc = arm926ejs_mrc,
|
||||
.mcr = arm926ejs_mcr,
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue