More instruction decoding fixes:
A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
parent
3bcf8a8a25
commit
49e2267f1f
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@ -2853,6 +2853,7 @@ static int t2ev_store_single(uint32_t opcode, uint32_t address,
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sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
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sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
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size, rt, rn, (int) opcode & 0x0f,
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size, rt, rn, (int) opcode & 0x0f,
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(int) (opcode >> 4) & 0x03);
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(int) (opcode >> 4) & 0x03);
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return ERROR_OK;
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imm12:
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imm12:
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immed = opcode & 0x0fff;
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immed = opcode & 0x0fff;
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@ -3354,18 +3355,21 @@ static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address,
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int rt = (opcode >> 12) & 0xf;
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int rt = (opcode >> 12) & 0xf;
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int op2 = (opcode >> 6) & 0x3f;
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int op2 = (opcode >> 6) & 0x3f;
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unsigned immed;
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unsigned immed;
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char *p1 = "]", *p2 = "";
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char *p1 = "", *p2 = "]";
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char *mnemonic;
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char *mnemonic;
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switch ((opcode >> 23) & 0x3) {
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switch ((opcode >> 23) & 0x3) {
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case 0:
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case 0:
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if ((rn & rt) == 0xf) {
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if ((rn & rt) == 0xf) {
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preload_immediate_t2:
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pld_literal:
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immed = opcode & 0xfff;
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immed = opcode & 0xfff;
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preload_immediate_t1:
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address = thumb_alignpc4(address);
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p1 = (opcode & (1 << 21)) ? "W" : "";
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if (opcode & (1 << 23))
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sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
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address += immed;
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p1, rn, immed, immed);
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else
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address -= immed;
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sprintf(cp, "PLD\tr%d, %#8.8" PRIx32,
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rt, address);
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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if (rn == 0x0f && rt != 0x0f) {
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if (rn == 0x0f && rt != 0x0f) {
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@ -3391,12 +3395,17 @@ ldrb_literal:
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if ((op2 & 0x3c) == 0x30) {
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if ((op2 & 0x3c) == 0x30) {
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if (rt == 0x0f) {
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if (rt == 0x0f) {
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immed = opcode & 0xff;
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immed = opcode & 0xff;
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goto preload_immediate_t1;
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immed = -immed;
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preload_immediate:
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p1 = (opcode & (1 << 21)) ? "W" : "";
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sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
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p1, rn, immed, immed);
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return ERROR_OK;
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}
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}
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mnemonic = "LDRB";
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mnemonic = "LDRB";
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ldrxb_immediate_t3:
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ldrxb_immediate_t3:
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immed = opcode & 0xff;
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immed = opcode & 0xff;
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if (opcode & 0x200)
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if (!(opcode & 0x200))
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immed = -immed;
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immed = -immed;
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/* two indexed modes will write back rn */
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/* two indexed modes will write back rn */
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@ -3432,8 +3441,12 @@ ldrxb_immediate_t2:
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}
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}
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break;
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break;
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case 1:
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case 1:
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if (rt == 0xf)
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if ((rn & rt) == 0xf)
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goto preload_immediate_t2;
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goto pld_literal;
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if (rt == 0xf) {
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immed = opcode & 0xfff;
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goto preload_immediate;
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}
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if (rn == 0x0f)
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if (rn == 0x0f)
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goto ldrb_literal;
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goto ldrb_literal;
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mnemonic = "LDRB.W";
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mnemonic = "LDRB.W";
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@ -3441,7 +3454,6 @@ ldrxb_immediate_t2:
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goto ldrxb_immediate_t2;
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goto ldrxb_immediate_t2;
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case 2:
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case 2:
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if ((rn & rt) == 0xf) {
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if ((rn & rt) == 0xf) {
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pli_immediate:
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immed = opcode & 0xfff;
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immed = opcode & 0xfff;
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address = thumb_alignpc4(address);
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address = thumb_alignpc4(address);
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if (opcode & (1 << 23))
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if (opcode & (1 << 23))
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@ -3466,7 +3478,7 @@ ldrsb_literal:
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break;
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break;
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if ((op2 & 0x3c) == 0x38) {
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if ((op2 & 0x3c) == 0x38) {
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immed = opcode & 0xff;
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immed = opcode & 0xff;
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sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %2.2x",
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sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %#2.2x",
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rt, rn, immed, immed);
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rt, rn, immed, immed);
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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@ -3474,8 +3486,8 @@ ldrsb_literal:
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if (rt == 0xf) {
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if (rt == 0xf) {
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immed = opcode & 0xff;
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immed = opcode & 0xff;
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immed = -immed; // pli
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immed = -immed; // pli
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sprintf(cp, "PLI\t[r%d, #-%d]\t; %2.2x",
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sprintf(cp, "PLI\t[r%d, #%d]\t; -%#2.2x",
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rn, immed, immed);
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rn, immed, -immed);
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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mnemonic = "LDRSB";
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mnemonic = "LDRSB";
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@ -3499,8 +3511,12 @@ ldrsb_literal:
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}
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}
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break;
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break;
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case 3:
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case 3:
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if (rt == 0xf)
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if (rt == 0xf) {
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goto pli_immediate;
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immed = opcode & 0xfff;
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sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3" PRIx32,
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rn, immed, immed);
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return ERROR_OK;
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}
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if (rn == 0xf)
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if (rn == 0xf)
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goto ldrsb_literal;
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goto ldrsb_literal;
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immed = opcode & 0xfff;
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immed = opcode & 0xfff;
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